pll.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
  4. */
  5. #define LOG_CATEGORY UCLASS_CLK
  6. #include <common.h>
  7. #include <dm.h>
  8. /* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
  9. #include <div64.h>
  10. #include <log.h>
  11. #include <serial.h>
  12. #include <asm/io.h>
  13. #include <dt-bindings/clock/k210-sysctl.h>
  14. #include <kendryte/pll.h>
  15. #include <linux/bitfield.h>
  16. #include <linux/clk-provider.h>
  17. #include <linux/delay.h>
  18. #include <linux/err.h>
  19. #define CLK_K210_PLL "k210_clk_pll"
  20. #ifdef CONFIG_CLK_K210_SET_RATE
  21. static int k210_pll_enable(struct clk *clk);
  22. static int k210_pll_disable(struct clk *clk);
  23. /*
  24. * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
  25. * General-Purpose PLL. The logical layout of the PLL with internal feedback is
  26. * approximately the following:
  27. *
  28. * +---------------+
  29. * |reference clock|
  30. * +---------------+
  31. * |
  32. * v
  33. * +--+
  34. * |/r|
  35. * +--+
  36. * |
  37. * v
  38. * +-------------+
  39. * |divided clock|
  40. * +-------------+
  41. * |
  42. * v
  43. * +--------------+
  44. * |phase detector|<---+
  45. * +--------------+ |
  46. * | |
  47. * v +--------------+
  48. * +---+ |feedback clock|
  49. * |VCO| +--------------+
  50. * +---+ ^
  51. * | +--+ |
  52. * +--->|/f|---+
  53. * | +--+
  54. * v
  55. * +---+
  56. * |/od|
  57. * +---+
  58. * |
  59. * v
  60. * +------+
  61. * |output|
  62. * +------+
  63. *
  64. * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
  65. * the effect of the division by f is to multiply the input frequency. The
  66. * equation for the output rate is
  67. * rate = (rate_in * f) / (r * od).
  68. * Moving knowns to one side of the equation, we get
  69. * rate / rate_in = f / (r * od)
  70. * Rearranging slightly,
  71. * abs_error = abs((rate / rate_in) - (f / (r * od))).
  72. * To get relative, error, we divide by the expected ratio
  73. * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
  74. * Simplifying,
  75. * error = abs(1 - f / (r * od)) / (rate / rate_in)
  76. * error = abs(1 - (f * rate_in) / (r * od * rate))
  77. * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate,
  78. * error = abs((f * inv_ratio) / (r * od) - 1)
  79. * This is the error used in evaluating parameters.
  80. *
  81. * r and od are four bits each, while f is six bits. Because r and od are
  82. * multiplied together, instead of the full 256 values possible if both bits
  83. * were used fully, there are only 97 distinct products. Combined with f, there
  84. * are 6208 theoretical settings for the PLL. However, most of these settings
  85. * can be ruled out immediately because they do not have the correct ratio.
  86. *
  87. * In addition to the constraint of approximating the desired ratio, parameters
  88. * must also keep internal pll frequencies within acceptable ranges. The divided
  89. * clock's minimum and maximum frequencies have a ratio of around 128. This
  90. * leaves fairly substantial room to work with, especially since the only
  91. * affected parameter is r. The VCO's minimum and maximum frequency have a ratio
  92. * of 5, which is considerably more restrictive.
  93. *
  94. * The r and od factors are stored in a table. This is to make it easy to find
  95. * the next-largest product. Some products have multiple factorizations, but
  96. * only when one factor has at least a 2.5x ratio to the factors of the other
  97. * factorization. This is because any smaller ratio would not make a difference
  98. * when ensuring the VCO's frequency is within spec.
  99. *
  100. * Throughout the calculation function, fixed point arithmetic is used. Because
  101. * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit
  102. * 32.32 fixed-point numbers are used to represent ratios. In general, to
  103. * implement division, the numerator is first multiplied by 2^32. This gives a
  104. * result where the whole number part is in the upper 32 bits, and the fraction
  105. * is in the lower 32 bits.
  106. *
  107. * In general, rounding is done to the closest integer. This helps find the best
  108. * approximation for the ratio. Rounding in one direction (e.g down) could cause
  109. * the function to miss a better ratio with one of the parameters increased by
  110. * one.
  111. */
  112. /*
  113. * The factors table was generated with the following python code:
  114. *
  115. * def p(x, y):
  116. * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5)
  117. *
  118. * factors = {}
  119. * for i in range(1, 17):
  120. * for j in range(1, 17):
  121. * fs = factors.get(i*j) or []
  122. * if fs == [] or all([
  123. * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y))
  124. * for (x, y) in fs]):
  125. * fs.append((i, j))
  126. * factors[i*j] = fs
  127. *
  128. * for k, l in sorted(factors.items()):
  129. * for v in l:
  130. * print("PACK(%s, %s)," % v)
  131. */
  132. #define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF))
  133. #define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1)
  134. #define UNPACK_OD(val) (((val) & 0xF) + 1)
  135. static const u8 factors[] = {
  136. PACK(1, 1),
  137. PACK(1, 2),
  138. PACK(1, 3),
  139. PACK(1, 4),
  140. PACK(1, 5),
  141. PACK(1, 6),
  142. PACK(1, 7),
  143. PACK(1, 8),
  144. PACK(1, 9),
  145. PACK(3, 3),
  146. PACK(1, 10),
  147. PACK(1, 11),
  148. PACK(1, 12),
  149. PACK(3, 4),
  150. PACK(1, 13),
  151. PACK(1, 14),
  152. PACK(1, 15),
  153. PACK(3, 5),
  154. PACK(1, 16),
  155. PACK(4, 4),
  156. PACK(2, 9),
  157. PACK(2, 10),
  158. PACK(3, 7),
  159. PACK(2, 11),
  160. PACK(2, 12),
  161. PACK(5, 5),
  162. PACK(2, 13),
  163. PACK(3, 9),
  164. PACK(2, 14),
  165. PACK(2, 15),
  166. PACK(2, 16),
  167. PACK(3, 11),
  168. PACK(5, 7),
  169. PACK(3, 12),
  170. PACK(3, 13),
  171. PACK(4, 10),
  172. PACK(3, 14),
  173. PACK(4, 11),
  174. PACK(3, 15),
  175. PACK(3, 16),
  176. PACK(7, 7),
  177. PACK(5, 10),
  178. PACK(4, 13),
  179. PACK(6, 9),
  180. PACK(5, 11),
  181. PACK(4, 14),
  182. PACK(4, 15),
  183. PACK(7, 9),
  184. PACK(4, 16),
  185. PACK(5, 13),
  186. PACK(6, 11),
  187. PACK(5, 14),
  188. PACK(6, 12),
  189. PACK(5, 15),
  190. PACK(7, 11),
  191. PACK(6, 13),
  192. PACK(5, 16),
  193. PACK(9, 9),
  194. PACK(6, 14),
  195. PACK(8, 11),
  196. PACK(6, 15),
  197. PACK(7, 13),
  198. PACK(6, 16),
  199. PACK(7, 14),
  200. PACK(9, 11),
  201. PACK(10, 10),
  202. PACK(8, 13),
  203. PACK(7, 15),
  204. PACK(9, 12),
  205. PACK(10, 11),
  206. PACK(7, 16),
  207. PACK(9, 13),
  208. PACK(8, 15),
  209. PACK(11, 11),
  210. PACK(9, 14),
  211. PACK(8, 16),
  212. PACK(10, 13),
  213. PACK(11, 12),
  214. PACK(9, 15),
  215. PACK(10, 14),
  216. PACK(11, 13),
  217. PACK(9, 16),
  218. PACK(10, 15),
  219. PACK(11, 14),
  220. PACK(12, 13),
  221. PACK(10, 16),
  222. PACK(11, 15),
  223. PACK(12, 14),
  224. PACK(13, 13),
  225. PACK(11, 16),
  226. PACK(12, 15),
  227. PACK(13, 14),
  228. PACK(12, 16),
  229. PACK(13, 15),
  230. PACK(14, 14),
  231. PACK(13, 16),
  232. PACK(14, 15),
  233. PACK(14, 16),
  234. PACK(15, 15),
  235. PACK(15, 16),
  236. PACK(16, 16),
  237. };
  238. TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
  239. struct k210_pll_config *best)
  240. {
  241. int i;
  242. s64 error, best_error;
  243. u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */
  244. u64 max_r;
  245. u64 r, f, od;
  246. /*
  247. * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the
  248. * VCO frequency. These are not the same limits as below because od can
  249. * reduce the output frequency by 16.
  250. */
  251. if (rate > 1750000000 || rate < 21250000)
  252. return -EINVAL;
  253. /* Similar restrictions on the input rate */
  254. if (rate_in > 1750000000 || rate_in < 13300000)
  255. return -EINVAL;
  256. ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in);
  257. inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
  258. /* Can't increase by more than 64 or reduce by more than 256 */
  259. if (rate > rate_in && ratio > (64ULL << 32))
  260. return -EINVAL;
  261. else if (rate <= rate_in && inv_ratio > (256ULL << 32))
  262. return -EINVAL;
  263. /*
  264. * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3
  265. * MHz. There is no minimum, since the only way to get a higher input
  266. * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs
  267. * cannot output frequencies greater than 1.75 GHz, the minimum would
  268. * never be greater than one.
  269. */
  270. max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000);
  271. /* Variables get immediately incremented, so start at -1th iteration */
  272. i = -1;
  273. f = 0;
  274. r = 0;
  275. od = 0;
  276. best_error = S64_MAX;
  277. error = best_error;
  278. /* do-while here so we always try at least one ratio */
  279. do {
  280. /*
  281. * Whether we swapped r and od while enforcing frequency limits
  282. */
  283. bool swapped = false;
  284. u64 last_od = od;
  285. u64 last_r = r;
  286. /*
  287. * Try the next largest value for f (or r and od) and
  288. * recalculate the other parameters based on that
  289. */
  290. if (rate > rate_in) {
  291. /*
  292. * Skip factors of the same product if we already tried
  293. * out that product
  294. */
  295. do {
  296. i++;
  297. r = UNPACK_R(factors[i]);
  298. od = UNPACK_OD(factors[i]);
  299. } while (i + 1 < ARRAY_SIZE(factors) &&
  300. r * od == last_r * last_od);
  301. /* Round close */
  302. f = (r * od * ratio + BIT(31)) >> 32;
  303. if (f > 64)
  304. f = 64;
  305. } else {
  306. u64 tmp = ++f * inv_ratio;
  307. bool round_up = !!(tmp & BIT(31));
  308. u32 goal = (tmp >> 32) + round_up;
  309. u32 err, last_err;
  310. /* Get the next r/od pair in factors */
  311. while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) {
  312. i++;
  313. r = UNPACK_R(factors[i]);
  314. od = UNPACK_OD(factors[i]);
  315. }
  316. /*
  317. * This is a case of double rounding. If we rounded up
  318. * above, we need to round down (in cases of ties) here.
  319. * This prevents off-by-one errors resulting from
  320. * choosing X+2 over X when X.Y rounds up to X+1 and
  321. * there is no r * od = X+1. For the converse, when X.Y
  322. * is rounded down to X, we should choose X+1 over X-1.
  323. */
  324. err = abs(r * od - goal);
  325. last_err = abs(last_r * last_od - goal);
  326. if (last_err < err || (round_up && last_err == err)) {
  327. i--;
  328. r = last_r;
  329. od = last_od;
  330. }
  331. }
  332. /*
  333. * Enforce limits on internal clock frequencies. If we
  334. * aren't in spec, try swapping r and od. If everything is
  335. * in-spec, calculate the relative error.
  336. */
  337. while (true) {
  338. /*
  339. * Whether the intermediate frequencies are out-of-spec
  340. */
  341. bool out_of_spec = false;
  342. if (r > max_r) {
  343. out_of_spec = true;
  344. } else {
  345. /*
  346. * There is no way to only divide once; we need
  347. * to examine the frequency with and without the
  348. * effect of od.
  349. */
  350. u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
  351. if (vco > 1750000000 || vco < 340000000)
  352. out_of_spec = true;
  353. }
  354. if (out_of_spec) {
  355. if (!swapped) {
  356. u64 tmp = r;
  357. r = od;
  358. od = tmp;
  359. swapped = true;
  360. continue;
  361. } else {
  362. /*
  363. * Try looking ahead to see if there are
  364. * additional factors for the same
  365. * product.
  366. */
  367. if (i + 1 < ARRAY_SIZE(factors)) {
  368. u64 new_r, new_od;
  369. i++;
  370. new_r = UNPACK_R(factors[i]);
  371. new_od = UNPACK_OD(factors[i]);
  372. if (r * od == new_r * new_od) {
  373. r = new_r;
  374. od = new_od;
  375. swapped = false;
  376. continue;
  377. }
  378. i--;
  379. }
  380. break;
  381. }
  382. }
  383. error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
  384. /* The lower 16 bits are spurious */
  385. error = abs((error - BIT(32))) >> 16;
  386. if (error < best_error) {
  387. best->r = r;
  388. best->f = f;
  389. best->od = od;
  390. best_error = error;
  391. }
  392. break;
  393. }
  394. } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
  395. if (best_error == S64_MAX)
  396. return -EINVAL;
  397. log_debug("best error %lld\n", best_error);
  398. return 0;
  399. }
  400. static ulong k210_pll_set_rate(struct clk *clk, ulong rate)
  401. {
  402. int err;
  403. long long rate_in = clk_get_parent_rate(clk);
  404. struct k210_pll_config config = {};
  405. struct k210_pll *pll = to_k210_pll(clk);
  406. u32 reg;
  407. if (rate_in < 0)
  408. return rate_in;
  409. log_debug("Calculating parameters with rate=%lu and rate_in=%lld\n",
  410. rate, rate_in);
  411. err = k210_pll_calc_config(rate, rate_in, &config);
  412. if (err)
  413. return err;
  414. log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
  415. /*
  416. * Don't use clk_disable as it might not actually disable the pll due to
  417. * refcounting
  418. */
  419. k210_pll_disable(clk);
  420. reg = readl(pll->reg);
  421. reg &= ~K210_PLL_CLKR
  422. & ~K210_PLL_CLKF
  423. & ~K210_PLL_CLKOD
  424. & ~K210_PLL_BWADJ;
  425. reg |= FIELD_PREP(K210_PLL_CLKR, config.r - 1)
  426. | FIELD_PREP(K210_PLL_CLKF, config.f - 1)
  427. | FIELD_PREP(K210_PLL_CLKOD, config.od - 1)
  428. | FIELD_PREP(K210_PLL_BWADJ, config.f - 1);
  429. writel(reg, pll->reg);
  430. err = k210_pll_enable(clk);
  431. if (err)
  432. return err;
  433. serial_setbrg();
  434. return clk_get_rate(clk);
  435. }
  436. #endif /* CONFIG_CLK_K210_SET_RATE */
  437. static ulong k210_pll_get_rate(struct clk *clk)
  438. {
  439. long long rate_in = clk_get_parent_rate(clk);
  440. struct k210_pll *pll = to_k210_pll(clk);
  441. u64 r, f, od;
  442. u32 reg = readl(pll->reg);
  443. if (rate_in < 0 || (reg & K210_PLL_BYPASS))
  444. return rate_in;
  445. if (!(reg & K210_PLL_PWRD))
  446. return 0;
  447. r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
  448. f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
  449. od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
  450. return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od);
  451. }
  452. /*
  453. * Wait for the PLL to be locked. If the PLL is not locked, try clearing the
  454. * slip before retrying
  455. */
  456. static void k210_pll_waitfor_lock(struct k210_pll *pll)
  457. {
  458. u32 mask = GENMASK(pll->width - 1, 0) << pll->shift;
  459. while (true) {
  460. u32 reg = readl(pll->lock);
  461. if ((reg & mask) == mask)
  462. break;
  463. reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP);
  464. writel(reg, pll->lock);
  465. }
  466. }
  467. /* Adapted from sysctl_pll_enable */
  468. static int k210_pll_enable(struct clk *clk)
  469. {
  470. struct k210_pll *pll = to_k210_pll(clk);
  471. u32 reg = readl(pll->reg);
  472. if ((reg | K210_PLL_PWRD) && !(reg | K210_PLL_RESET))
  473. return 0;
  474. reg |= K210_PLL_PWRD;
  475. writel(reg, pll->reg);
  476. /* Ensure reset is low before asserting it */
  477. reg &= ~K210_PLL_RESET;
  478. writel(reg, pll->reg);
  479. reg |= K210_PLL_RESET;
  480. writel(reg, pll->reg);
  481. nop();
  482. nop();
  483. reg &= ~K210_PLL_RESET;
  484. writel(reg, pll->reg);
  485. k210_pll_waitfor_lock(pll);
  486. reg &= ~K210_PLL_BYPASS;
  487. writel(reg, pll->reg);
  488. return 0;
  489. }
  490. static int k210_pll_disable(struct clk *clk)
  491. {
  492. struct k210_pll *pll = to_k210_pll(clk);
  493. u32 reg = readl(pll->reg);
  494. /*
  495. * Bypassing before powering off is important so child clocks don't stop
  496. * working. This is especially important for pll0, the indirect parent
  497. * of the cpu clock.
  498. */
  499. reg |= K210_PLL_BYPASS;
  500. writel(reg, pll->reg);
  501. reg &= ~K210_PLL_PWRD;
  502. writel(reg, pll->reg);
  503. return 0;
  504. }
  505. const struct clk_ops k210_pll_ops = {
  506. .get_rate = k210_pll_get_rate,
  507. #ifdef CONFIG_CLK_K210_SET_RATE
  508. .set_rate = k210_pll_set_rate,
  509. #endif
  510. .enable = k210_pll_enable,
  511. .disable = k210_pll_disable,
  512. };
  513. struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
  514. struct k210_pll *pll)
  515. {
  516. int ret;
  517. struct clk *clk = &pll->clk;
  518. ret = clk_register(clk, CLK_K210_PLL, name, parent_name);
  519. if (ret)
  520. return ERR_PTR(ret);
  521. return clk;
  522. }
  523. struct clk *k210_register_pll(const char *name, const char *parent_name,
  524. void __iomem *reg, void __iomem *lock, u8 shift,
  525. u8 width)
  526. {
  527. struct clk *clk;
  528. struct k210_pll *pll;
  529. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  530. if (!pll)
  531. return ERR_PTR(-ENOMEM);
  532. pll->reg = reg;
  533. pll->lock = lock;
  534. pll->shift = shift;
  535. pll->width = width;
  536. clk = k210_register_pll_struct(name, parent_name, pll);
  537. if (IS_ERR(clk))
  538. kfree(pll);
  539. return clk;
  540. }
  541. U_BOOT_DRIVER(k210_pll) = {
  542. .name = CLK_K210_PLL,
  543. .id = UCLASS_CLK,
  544. .ops = &k210_pll_ops,
  545. };