clk_stm32f.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <stm32_rcc.h>
  11. #include <linux/bitops.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/stm32.h>
  14. #include <asm/arch/stm32_pwr.h>
  15. #include <dt-bindings/mfd/stm32f7-rcc.h>
  16. #define RCC_CR_HSION BIT(0)
  17. #define RCC_CR_HSEON BIT(16)
  18. #define RCC_CR_HSERDY BIT(17)
  19. #define RCC_CR_HSEBYP BIT(18)
  20. #define RCC_CR_CSSON BIT(19)
  21. #define RCC_CR_PLLON BIT(24)
  22. #define RCC_CR_PLLRDY BIT(25)
  23. #define RCC_CR_PLLSAION BIT(28)
  24. #define RCC_CR_PLLSAIRDY BIT(29)
  25. #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
  26. #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
  27. #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
  28. #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
  29. #define RCC_PLLCFGR_PLLSRC BIT(22)
  30. #define RCC_PLLCFGR_PLLM_SHIFT 0
  31. #define RCC_PLLCFGR_PLLN_SHIFT 6
  32. #define RCC_PLLCFGR_PLLP_SHIFT 16
  33. #define RCC_PLLCFGR_PLLQ_SHIFT 24
  34. #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
  35. #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
  36. #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
  37. #define RCC_CFGR_SW0 BIT(0)
  38. #define RCC_CFGR_SW1 BIT(1)
  39. #define RCC_CFGR_SW_MASK GENMASK(1, 0)
  40. #define RCC_CFGR_SW_HSI 0
  41. #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
  42. #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
  43. #define RCC_CFGR_SWS0 BIT(2)
  44. #define RCC_CFGR_SWS1 BIT(3)
  45. #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
  46. #define RCC_CFGR_SWS_HSI 0
  47. #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
  48. #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
  49. #define RCC_CFGR_HPRE_SHIFT 4
  50. #define RCC_CFGR_PPRE1_SHIFT 10
  51. #define RCC_CFGR_PPRE2_SHIFT 13
  52. #define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
  53. #define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
  54. #define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
  55. #define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28)
  56. #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
  57. #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
  58. #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
  59. #define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
  60. #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
  61. #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
  62. #define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28)
  63. #define RCC_DCKCFGRX_TIMPRE BIT(24)
  64. #define RCC_DCKCFGRX_CK48MSEL BIT(27)
  65. #define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
  66. #define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
  67. #define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16
  68. #define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16)
  69. #define RCC_DCKCFGR_PLLSAIDIVR_2 0
  70. /*
  71. * RCC AHB1ENR specific definitions
  72. */
  73. #define RCC_AHB1ENR_ETHMAC_EN BIT(25)
  74. #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
  75. #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
  76. /*
  77. * RCC APB1ENR specific definitions
  78. */
  79. #define RCC_APB1ENR_TIM2EN BIT(0)
  80. #define RCC_APB1ENR_PWREN BIT(28)
  81. /*
  82. * RCC APB2ENR specific definitions
  83. */
  84. #define RCC_APB2ENR_SYSCFGEN BIT(14)
  85. #define RCC_APB2ENR_SAI1EN BIT(22)
  86. enum pllsai_div {
  87. PLLSAIP,
  88. PLLSAIQ,
  89. PLLSAIR,
  90. };
  91. static const struct stm32_clk_info stm32f4_clk_info = {
  92. /* 180 MHz */
  93. .sys_pll_psc = {
  94. .pll_n = 360,
  95. .pll_p = 2,
  96. .pll_q = 8,
  97. .ahb_psc = AHB_PSC_1,
  98. .apb1_psc = APB_PSC_4,
  99. .apb2_psc = APB_PSC_2,
  100. },
  101. .has_overdrive = false,
  102. .v2 = false,
  103. };
  104. static const struct stm32_clk_info stm32f7_clk_info = {
  105. /* 200 MHz */
  106. .sys_pll_psc = {
  107. .pll_n = 400,
  108. .pll_p = 2,
  109. .pll_q = 8,
  110. .ahb_psc = AHB_PSC_1,
  111. .apb1_psc = APB_PSC_4,
  112. .apb2_psc = APB_PSC_2,
  113. },
  114. .has_overdrive = true,
  115. .v2 = true,
  116. };
  117. struct stm32_clk {
  118. struct stm32_rcc_regs *base;
  119. struct stm32_pwr_regs *pwr_regs;
  120. struct stm32_clk_info info;
  121. unsigned long hse_rate;
  122. bool pllsaip;
  123. };
  124. #ifdef CONFIG_VIDEO_STM32
  125. static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 };
  126. #endif
  127. static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
  128. static int configure_clocks(struct udevice *dev)
  129. {
  130. struct stm32_clk *priv = dev_get_priv(dev);
  131. struct stm32_rcc_regs *regs = priv->base;
  132. struct stm32_pwr_regs *pwr = priv->pwr_regs;
  133. struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
  134. /* Reset RCC configuration */
  135. setbits_le32(&regs->cr, RCC_CR_HSION);
  136. writel(0, &regs->cfgr); /* Reset CFGR */
  137. clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
  138. | RCC_CR_PLLON | RCC_CR_PLLSAION));
  139. writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
  140. clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
  141. writel(0, &regs->cir); /* Disable all interrupts */
  142. /* Configure for HSE+PLL operation */
  143. setbits_le32(&regs->cr, RCC_CR_HSEON);
  144. while (!(readl(&regs->cr) & RCC_CR_HSERDY))
  145. ;
  146. setbits_le32(&regs->cfgr, ((
  147. sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
  148. | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
  149. | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
  150. /* Configure the main PLL */
  151. setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
  152. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
  153. sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
  154. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
  155. sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
  156. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
  157. ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
  158. clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
  159. sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
  160. /* configure SDMMC clock */
  161. if (priv->info.v2) { /*stm32f7 case */
  162. if (priv->pllsaip)
  163. /* select PLLSAIP as 48MHz clock source */
  164. setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
  165. else
  166. /* select PLLQ as 48MHz clock source */
  167. clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
  168. /* select 48MHz as SDMMC1 clock source */
  169. clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
  170. /* select 48MHz as SDMMC2 clock source */
  171. clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
  172. } else { /* stm32f4 case */
  173. if (priv->pllsaip)
  174. /* select PLLSAIP as 48MHz clock source */
  175. setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
  176. else
  177. /* select PLLQ as 48MHz clock source */
  178. clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
  179. /* select 48MHz as SDMMC1 clock source */
  180. clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
  181. }
  182. /*
  183. * Configure the SAI PLL to generate LTDC pixel clock and
  184. * 48 Mhz for SDMMC and USB
  185. */
  186. clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIP_MASK,
  187. RCC_PLLSAICFGR_PLLSAIP_4);
  188. clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
  189. RCC_PLLSAICFGR_PLLSAIR_3);
  190. clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK,
  191. 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT);
  192. clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
  193. RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
  194. /* Enable the main PLL */
  195. setbits_le32(&regs->cr, RCC_CR_PLLON);
  196. while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
  197. ;
  198. /* Enable the SAI PLL */
  199. setbits_le32(&regs->cr, RCC_CR_PLLSAION);
  200. while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
  201. ;
  202. setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
  203. if (priv->info.has_overdrive) {
  204. /*
  205. * Enable high performance mode
  206. * System frequency up to 200 MHz
  207. */
  208. setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
  209. /* Infinite wait! */
  210. while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
  211. ;
  212. /* Enable the Over-drive switch */
  213. setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
  214. /* Infinite wait! */
  215. while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
  216. ;
  217. }
  218. stm32_flash_latency_cfg(5);
  219. clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
  220. setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
  221. while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
  222. RCC_CFGR_SWS_PLL)
  223. ;
  224. #ifdef CONFIG_ETH_DESIGNWARE
  225. /* gate the SYSCFG clock, needed to set RMII ethernet interface */
  226. setbits_le32(&regs->apb2enr, RCC_APB2ENR_SYSCFGEN);
  227. #endif
  228. return 0;
  229. }
  230. static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
  231. {
  232. struct stm32_rcc_regs *regs = priv->base;
  233. if (priv->info.v2) /*stm32f7 case */
  234. return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
  235. else
  236. return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
  237. }
  238. static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
  239. {
  240. struct stm32_rcc_regs *regs = priv->base;
  241. u16 pllm, pllsain;
  242. pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
  243. pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
  244. >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
  245. return ((priv->hse_rate / pllm) * pllsain);
  246. }
  247. static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
  248. enum pllsai_div output)
  249. {
  250. struct stm32_rcc_regs *regs = priv->base;
  251. u16 pll_div_output;
  252. switch (output) {
  253. case PLLSAIP:
  254. pll_div_output = ((((readl(&regs->pllsaicfgr)
  255. & RCC_PLLSAICFGR_PLLSAIP_MASK)
  256. >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
  257. break;
  258. case PLLSAIQ:
  259. pll_div_output = (readl(&regs->pllsaicfgr)
  260. & RCC_PLLSAICFGR_PLLSAIQ_MASK)
  261. >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
  262. break;
  263. case PLLSAIR:
  264. pll_div_output = (readl(&regs->pllsaicfgr)
  265. & RCC_PLLSAICFGR_PLLSAIR_MASK)
  266. >> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
  267. break;
  268. default:
  269. pr_err("incorrect PLLSAI output %d\n", output);
  270. return -EINVAL;
  271. }
  272. return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
  273. }
  274. static bool stm32_get_timpre(struct stm32_clk *priv)
  275. {
  276. struct stm32_rcc_regs *regs = priv->base;
  277. u32 val;
  278. if (priv->info.v2) /*stm32f7 case */
  279. val = readl(&regs->dckcfgr2);
  280. else
  281. val = readl(&regs->dckcfgr);
  282. /* get timer prescaler */
  283. return !!(val & RCC_DCKCFGRX_TIMPRE);
  284. }
  285. static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
  286. {
  287. u8 shift;
  288. /* Prescaler table lookups for clock computation */
  289. u8 ahb_psc_table[16] = {
  290. 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
  291. };
  292. shift = ahb_psc_table[(
  293. (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
  294. >> RCC_CFGR_HPRE_SHIFT)];
  295. return sysclk >> shift;
  296. };
  297. static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
  298. {
  299. /* Prescaler table lookups for clock computation */
  300. u8 apb_psc_table[8] = {
  301. 0, 0, 0, 0, 1, 2, 3, 4
  302. };
  303. if (apb == APB1)
  304. return apb_psc_table[(
  305. (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
  306. >> RCC_CFGR_PPRE1_SHIFT)];
  307. else /* APB2 */
  308. return apb_psc_table[(
  309. (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
  310. >> RCC_CFGR_PPRE2_SHIFT)];
  311. };
  312. static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
  313. enum apb apb)
  314. {
  315. struct stm32_rcc_regs *regs = priv->base;
  316. u8 shift = stm32_get_apb_shift(regs, apb);
  317. if (stm32_get_timpre(priv))
  318. /*
  319. * if APB prescaler is configured to a
  320. * division factor of 1, 2 or 4
  321. */
  322. switch (shift) {
  323. case 0:
  324. case 1:
  325. case 2:
  326. return stm32_get_hclk_rate(regs, sysclk);
  327. default:
  328. return (sysclk >> shift) * 4;
  329. }
  330. else
  331. /*
  332. * if APB prescaler is configured to a
  333. * division factor of 1
  334. */
  335. if (shift == 0)
  336. return sysclk;
  337. else
  338. return (sysclk >> shift) * 2;
  339. };
  340. static ulong stm32_clk_get_rate(struct clk *clk)
  341. {
  342. struct stm32_clk *priv = dev_get_priv(clk->dev);
  343. struct stm32_rcc_regs *regs = priv->base;
  344. u32 sysclk = 0;
  345. u32 vco;
  346. u32 sdmmcxsel_bit;
  347. u32 saidivr;
  348. u32 pllsai_rate;
  349. u16 pllm, plln, pllp, pllq;
  350. if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
  351. RCC_CFGR_SWS_PLL) {
  352. pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
  353. plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
  354. >> RCC_PLLCFGR_PLLN_SHIFT);
  355. pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
  356. >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
  357. pllq = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
  358. >> RCC_PLLCFGR_PLLQ_SHIFT);
  359. vco = (priv->hse_rate / pllm) * plln;
  360. sysclk = vco / pllp;
  361. } else {
  362. return -EINVAL;
  363. }
  364. switch (clk->id) {
  365. /*
  366. * AHB CLOCK: 3 x 32 bits consecutive registers are used :
  367. * AHB1, AHB2 and AHB3
  368. */
  369. case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
  370. return stm32_get_hclk_rate(regs, sysclk);
  371. /* APB1 CLOCK */
  372. case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
  373. /* For timer clock, an additionnal prescaler is used*/
  374. switch (clk->id) {
  375. case STM32F7_APB1_CLOCK(TIM2):
  376. case STM32F7_APB1_CLOCK(TIM3):
  377. case STM32F7_APB1_CLOCK(TIM4):
  378. case STM32F7_APB1_CLOCK(TIM5):
  379. case STM32F7_APB1_CLOCK(TIM6):
  380. case STM32F7_APB1_CLOCK(TIM7):
  381. case STM32F7_APB1_CLOCK(TIM12):
  382. case STM32F7_APB1_CLOCK(TIM13):
  383. case STM32F7_APB1_CLOCK(TIM14):
  384. return stm32_get_timer_rate(priv, sysclk, APB1);
  385. }
  386. return (sysclk >> stm32_get_apb_shift(regs, APB1));
  387. /* APB2 CLOCK */
  388. case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI):
  389. switch (clk->id) {
  390. /*
  391. * particular case for SDMMC1 and SDMMC2 :
  392. * 48Mhz source clock can be from main PLL or from
  393. * PLLSAIP
  394. */
  395. case STM32F7_APB2_CLOCK(SDMMC1):
  396. case STM32F7_APB2_CLOCK(SDMMC2):
  397. if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
  398. sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
  399. else
  400. sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
  401. if (readl(&regs->dckcfgr2) & sdmmcxsel_bit)
  402. /* System clock is selected as SDMMC1 clock */
  403. return sysclk;
  404. /*
  405. * 48 MHz can be generated by either PLLSAIP
  406. * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
  407. */
  408. if (stm32_clk_get_ck48msel(priv))
  409. return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
  410. else
  411. return (vco / pllq);
  412. break;
  413. /* For timer clock, an additionnal prescaler is used*/
  414. case STM32F7_APB2_CLOCK(TIM1):
  415. case STM32F7_APB2_CLOCK(TIM8):
  416. case STM32F7_APB2_CLOCK(TIM9):
  417. case STM32F7_APB2_CLOCK(TIM10):
  418. case STM32F7_APB2_CLOCK(TIM11):
  419. return stm32_get_timer_rate(priv, sysclk, APB2);
  420. break;
  421. /* particular case for LTDC clock */
  422. case STM32F7_APB2_CLOCK(LTDC):
  423. saidivr = readl(&regs->dckcfgr);
  424. saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK)
  425. >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT;
  426. pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
  427. return pllsai_rate / pllsaidivr_table[saidivr];
  428. }
  429. return (sysclk >> stm32_get_apb_shift(regs, APB2));
  430. default:
  431. pr_err("clock index %ld out of range\n", clk->id);
  432. return -EINVAL;
  433. }
  434. }
  435. static ulong stm32_set_rate(struct clk *clk, ulong rate)
  436. {
  437. #ifdef CONFIG_VIDEO_STM32
  438. struct stm32_clk *priv = dev_get_priv(clk->dev);
  439. struct stm32_rcc_regs *regs = priv->base;
  440. u32 pllsair_rate, pllsai_vco_rate, current_rate;
  441. u32 best_div, best_diff, diff;
  442. u16 div;
  443. u8 best_plldivr, best_pllsaidivr;
  444. u8 i, j;
  445. bool found = false;
  446. /* Only set_rate for LTDC clock is implemented */
  447. if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
  448. pr_err("set_rate not implemented for clock index %ld\n",
  449. clk->id);
  450. return 0;
  451. }
  452. if (rate == stm32_clk_get_rate(clk))
  453. /* already set to requested rate */
  454. return rate;
  455. /* get the current PLLSAIR output freq */
  456. pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
  457. best_div = pllsair_rate / rate;
  458. /* look into pllsaidivr_table if this divider is available*/
  459. for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
  460. if (best_div == pllsaidivr_table[i]) {
  461. /* set pll_saidivr with found value */
  462. clrsetbits_le32(&regs->dckcfgr,
  463. RCC_DCKCFGR_PLLSAIDIVR_MASK,
  464. pllsaidivr_table[i]);
  465. return rate;
  466. }
  467. /*
  468. * As no pllsaidivr value is suitable to obtain requested freq,
  469. * test all combination of pllsaidivr * pllsair and find the one
  470. * which give freq closest to requested rate.
  471. */
  472. pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv);
  473. best_diff = ULONG_MAX;
  474. best_pllsaidivr = 0;
  475. best_plldivr = 0;
  476. /*
  477. * start at index 2 of plldivr_table as divider value at index 0
  478. * and 1 are 0)
  479. */
  480. for (i = 2; i < sizeof(plldivr_table); i++) {
  481. for (j = 0; j < sizeof(pllsaidivr_table); j++) {
  482. div = plldivr_table[i] * pllsaidivr_table[j];
  483. current_rate = pllsai_vco_rate / div;
  484. /* perfect combination is found ? */
  485. if (current_rate == rate) {
  486. best_pllsaidivr = j;
  487. best_plldivr = i;
  488. found = true;
  489. break;
  490. }
  491. diff = (current_rate > rate) ?
  492. current_rate - rate : rate - current_rate;
  493. /* found a better combination ? */
  494. if (diff < best_diff) {
  495. best_diff = diff;
  496. best_pllsaidivr = j;
  497. best_plldivr = i;
  498. }
  499. }
  500. if (found)
  501. break;
  502. }
  503. /* Disable the SAI PLL */
  504. clrbits_le32(&regs->cr, RCC_CR_PLLSAION);
  505. /* set pll_saidivr with found value */
  506. clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
  507. best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
  508. /* set pllsair with found value */
  509. clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
  510. plldivr_table[best_plldivr]
  511. << RCC_PLLSAICFGR_PLLSAIR_SHIFT);
  512. /* Enable the SAI PLL */
  513. setbits_le32(&regs->cr, RCC_CR_PLLSAION);
  514. while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
  515. ;
  516. div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr];
  517. return pllsai_vco_rate / div;
  518. #else
  519. return 0;
  520. #endif
  521. }
  522. static int stm32_clk_enable(struct clk *clk)
  523. {
  524. struct stm32_clk *priv = dev_get_priv(clk->dev);
  525. struct stm32_rcc_regs *regs = priv->base;
  526. u32 offset = clk->id / 32;
  527. u32 bit_index = clk->id % 32;
  528. debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
  529. __func__, clk->id, offset, bit_index);
  530. setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
  531. return 0;
  532. }
  533. static int stm32_clk_probe(struct udevice *dev)
  534. {
  535. struct ofnode_phandle_args args;
  536. struct udevice *fixed_clock_dev = NULL;
  537. struct clk clk;
  538. int err;
  539. debug("%s\n", __func__);
  540. struct stm32_clk *priv = dev_get_priv(dev);
  541. fdt_addr_t addr;
  542. addr = dev_read_addr(dev);
  543. if (addr == FDT_ADDR_T_NONE)
  544. return -EINVAL;
  545. priv->base = (struct stm32_rcc_regs *)addr;
  546. priv->pllsaip = true;
  547. switch (dev_get_driver_data(dev)) {
  548. case STM32F42X:
  549. priv->pllsaip = false;
  550. /* fallback into STM32F469 case */
  551. case STM32F469:
  552. memcpy(&priv->info, &stm32f4_clk_info,
  553. sizeof(struct stm32_clk_info));
  554. break;
  555. case STM32F7:
  556. memcpy(&priv->info, &stm32f7_clk_info,
  557. sizeof(struct stm32_clk_info));
  558. break;
  559. default:
  560. return -EINVAL;
  561. }
  562. /* retrieve HSE frequency (external oscillator) */
  563. err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
  564. &fixed_clock_dev);
  565. if (err) {
  566. pr_err("Can't find fixed clock (%d)", err);
  567. return err;
  568. }
  569. err = clk_request(fixed_clock_dev, &clk);
  570. if (err) {
  571. pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
  572. err);
  573. return err;
  574. }
  575. /*
  576. * set pllm factor accordingly to the external oscillator
  577. * frequency (HSE). For STM32F4 and STM32F7, we want VCO
  578. * freq at 1MHz
  579. * if input PLL frequency is 25Mhz, divide it by 25
  580. */
  581. clk.id = 0;
  582. priv->hse_rate = clk_get_rate(&clk);
  583. if (priv->hse_rate < 1000000) {
  584. pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
  585. priv->hse_rate);
  586. return -EINVAL;
  587. }
  588. priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
  589. if (priv->info.has_overdrive) {
  590. err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
  591. &args);
  592. if (err) {
  593. debug("%s: can't find syscon device (%d)\n", __func__,
  594. err);
  595. return err;
  596. }
  597. priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
  598. }
  599. configure_clocks(dev);
  600. return 0;
  601. }
  602. static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
  603. {
  604. debug("%s(clk=%p)\n", __func__, clk);
  605. if (args->args_count != 2) {
  606. debug("Invaild args_count: %d\n", args->args_count);
  607. return -EINVAL;
  608. }
  609. if (args->args_count)
  610. clk->id = args->args[1];
  611. else
  612. clk->id = 0;
  613. return 0;
  614. }
  615. static struct clk_ops stm32_clk_ops = {
  616. .of_xlate = stm32_clk_of_xlate,
  617. .enable = stm32_clk_enable,
  618. .get_rate = stm32_clk_get_rate,
  619. .set_rate = stm32_set_rate,
  620. };
  621. U_BOOT_DRIVER(stm32fx_clk) = {
  622. .name = "stm32fx_rcc_clock",
  623. .id = UCLASS_CLK,
  624. .ops = &stm32_clk_ops,
  625. .probe = stm32_clk_probe,
  626. .priv_auto_alloc_size = sizeof(struct stm32_clk),
  627. .flags = DM_FLAG_PRE_RELOC,
  628. };