clk_octeon.c 1.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 Stefan Roese <sr@denx.de>
  4. */
  5. #include <clk-uclass.h>
  6. #include <dm.h>
  7. #include <dt-bindings/clock/octeon-clock.h>
  8. DECLARE_GLOBAL_DATA_PTR;
  9. struct octeon_clk_priv {
  10. u64 core_clk;
  11. u64 io_clk;
  12. };
  13. static int octeon_clk_enable(struct clk *clk)
  14. {
  15. /* Nothing to do on Octeon */
  16. return 0;
  17. }
  18. static ulong octeon_clk_get_rate(struct clk *clk)
  19. {
  20. struct octeon_clk_priv *priv = dev_get_priv(clk->dev);
  21. switch (clk->id) {
  22. case OCTEON_CLK_CORE:
  23. return priv->core_clk;
  24. case OCTEON_CLK_IO:
  25. return priv->io_clk;
  26. default:
  27. return 0;
  28. }
  29. return 0;
  30. }
  31. static struct clk_ops octeon_clk_ops = {
  32. .enable = octeon_clk_enable,
  33. .get_rate = octeon_clk_get_rate,
  34. };
  35. static const struct udevice_id octeon_clk_ids[] = {
  36. { .compatible = "mrvl,octeon-clk" },
  37. { /* sentinel */ }
  38. };
  39. static int octeon_clk_probe(struct udevice *dev)
  40. {
  41. struct octeon_clk_priv *priv = dev_get_priv(dev);
  42. /*
  43. * The clock values are already read into GD, lets just store them
  44. * in priv data
  45. */
  46. priv->core_clk = gd->cpu_clk;
  47. priv->io_clk = gd->bus_clk;
  48. return 0;
  49. }
  50. U_BOOT_DRIVER(clk_octeon) = {
  51. .name = "clk_octeon",
  52. .id = UCLASS_CLK,
  53. .of_match = octeon_clk_ids,
  54. .ops = &octeon_clk_ops,
  55. .probe = octeon_clk_probe,
  56. .priv_auto_alloc_size = sizeof(struct octeon_clk_priv),
  57. };