wrpll-cln28hpc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018-2019 SiFive, Inc.
  4. * Wesley Terpstra
  5. * Paul Walmsley
  6. *
  7. * This library supports configuration parsing and reprogramming of
  8. * the CLN28HPC variant of the Analog Bits Wide Range PLL. The
  9. * intention is for this library to be reusable for any device that
  10. * integrates this PLL; thus the register structure and programming
  11. * details are expected to be provided by a separate IP block driver.
  12. *
  13. * The bulk of this code is primarily useful for clock configurations
  14. * that must operate at arbitrary rates, as opposed to clock configurations
  15. * that are restricted by software or manufacturer guidance to a small,
  16. * pre-determined set of performance points.
  17. *
  18. * References:
  19. * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
  20. * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
  21. * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
  22. */
  23. #include <linux/bug.h>
  24. #include <linux/err.h>
  25. #include <linux/log2.h>
  26. #include <linux/math64.h>
  27. #include <linux/clk/analogbits-wrpll-cln28hpc.h>
  28. /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
  29. #define MIN_INPUT_FREQ 7000000
  30. /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
  31. #define MAX_INPUT_FREQ 600000000
  32. /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
  33. #define MIN_POST_DIVR_FREQ 7000000
  34. /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
  35. #define MAX_POST_DIVR_FREQ 200000000
  36. /* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */
  37. #define MIN_VCO_FREQ 2400000000UL
  38. /* MAX_VCO_FREQ: maximum VCO frequency, in Hz (Fvco_max) */
  39. #define MAX_VCO_FREQ 4800000000ULL
  40. /* MAX_DIVQ_DIVISOR: maximum output divisor. Selected by DIVQ = 6 */
  41. #define MAX_DIVQ_DIVISOR 64
  42. /* MAX_DIVR_DIVISOR: maximum reference divisor. Selected by DIVR = 63 */
  43. #define MAX_DIVR_DIVISOR 64
  44. /* MAX_LOCK_US: maximum PLL lock time, in microseconds (tLOCK_max) */
  45. #define MAX_LOCK_US 70
  46. /*
  47. * ROUND_SHIFT: number of bits to shift to avoid precision loss in the rounding
  48. * algorithm
  49. */
  50. #define ROUND_SHIFT 20
  51. /*
  52. * Private functions
  53. */
  54. /**
  55. * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
  56. * @post_divr_freq: input clock rate after the R divider
  57. *
  58. * Select the value to be presented to the PLL RANGE input signals, based
  59. * on the input clock frequency after the post-R-divider @post_divr_freq.
  60. * This code follows the recommendations in the PLL datasheet for filter
  61. * range selection.
  62. *
  63. * Return: The RANGE value to be presented to the PLL configuration inputs,
  64. * or a negative return code upon error.
  65. */
  66. static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
  67. {
  68. if (post_divr_freq < MIN_POST_DIVR_FREQ ||
  69. post_divr_freq > MAX_POST_DIVR_FREQ) {
  70. WARN(1, "%s: post-divider reference freq out of range: %lu",
  71. __func__, post_divr_freq);
  72. return -ERANGE;
  73. }
  74. switch (post_divr_freq) {
  75. case 0 ... 10999999:
  76. return 1;
  77. case 11000000 ... 17999999:
  78. return 2;
  79. case 18000000 ... 29999999:
  80. return 3;
  81. case 30000000 ... 49999999:
  82. return 4;
  83. case 50000000 ... 79999999:
  84. return 5;
  85. case 80000000 ... 129999999:
  86. return 6;
  87. }
  88. return 7;
  89. }
  90. /**
  91. * __wrpll_calc_fbdiv() - return feedback fixed divide value
  92. * @c: ptr to a struct wrpll_cfg record to read from
  93. *
  94. * The internal feedback path includes a fixed by-two divider; the
  95. * external feedback path does not. Return the appropriate divider
  96. * value (2 or 1) depending on whether internal or external feedback
  97. * is enabled. This code doesn't test for invalid configurations
  98. * (e.g. both or neither of WRPLL_FLAGS_*_FEEDBACK are set); it relies
  99. * on the caller to do so.
  100. *
  101. * Context: Any context. Caller must protect the memory pointed to by
  102. * @c from simultaneous modification.
  103. *
  104. * Return: 2 if internal feedback is enabled or 1 if external feedback
  105. * is enabled.
  106. */
  107. static u8 __wrpll_calc_fbdiv(const struct wrpll_cfg *c)
  108. {
  109. return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1;
  110. }
  111. /**
  112. * __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate
  113. * @target_rate: target PLL output clock rate
  114. * @vco_rate: pointer to a u64 to store the computed VCO rate into
  115. *
  116. * Determine a reasonable value for the PLL Q post-divider, based on the
  117. * target output rate @target_rate for the PLL. Along with returning the
  118. * computed Q divider value as the return value, this function stores the
  119. * desired target VCO rate into the variable pointed to by @vco_rate.
  120. *
  121. * Context: Any context. Caller must protect the memory pointed to by
  122. * @vco_rate from simultaneous access or modification.
  123. *
  124. * Return: a positive integer DIVQ value to be programmed into the hardware
  125. * upon success, or 0 upon error (since 0 is an invalid DIVQ value)
  126. */
  127. static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate)
  128. {
  129. u64 s;
  130. u8 divq = 0;
  131. if (!vco_rate) {
  132. WARN_ON(1);
  133. goto wcd_out;
  134. }
  135. s = div_u64(MAX_VCO_FREQ, target_rate);
  136. if (s <= 1) {
  137. divq = 1;
  138. *vco_rate = MAX_VCO_FREQ;
  139. } else if (s > MAX_DIVQ_DIVISOR) {
  140. divq = ilog2(MAX_DIVQ_DIVISOR);
  141. *vco_rate = MIN_VCO_FREQ;
  142. } else {
  143. divq = ilog2(s);
  144. *vco_rate = (u64)target_rate << divq;
  145. }
  146. wcd_out:
  147. return divq;
  148. }
  149. /**
  150. * __wrpll_update_parent_rate() - update PLL data when parent rate changes
  151. * @c: ptr to a struct wrpll_cfg record to write PLL data to
  152. * @parent_rate: PLL input refclk rate (pre-R-divider)
  153. *
  154. * Pre-compute some data used by the PLL configuration algorithm when
  155. * the PLL's reference clock rate changes. The intention is to avoid
  156. * computation when the parent rate remains constant - expected to be
  157. * the common case.
  158. *
  159. * Returns: 0 upon success or -ERANGE if the reference clock rate is
  160. * out of range.
  161. */
  162. static int __wrpll_update_parent_rate(struct wrpll_cfg *c,
  163. unsigned long parent_rate)
  164. {
  165. u8 max_r_for_parent;
  166. if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
  167. return -ERANGE;
  168. c->parent_rate = parent_rate;
  169. max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
  170. c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);
  171. c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);
  172. return 0;
  173. }
  174. /**
  175. * wrpll_configure() - compute PLL configuration for a target rate
  176. * @c: ptr to a struct wrpll_cfg record to write into
  177. * @target_rate: target PLL output clock rate (post-Q-divider)
  178. * @parent_rate: PLL input refclk rate (pre-R-divider)
  179. *
  180. * Compute the appropriate PLL signal configuration values and store
  181. * in PLL context @c. PLL reprogramming is not glitchless, so the
  182. * caller should switch any downstream logic to a different clock
  183. * source or clock-gate it before presenting these values to the PLL
  184. * configuration signals.
  185. *
  186. * The caller must pass this function a pre-initialized struct
  187. * wrpll_cfg record: either initialized to zero (with the
  188. * exception of the .name and .flags fields) or read from the PLL.
  189. *
  190. * Context: Any context. Caller must protect the memory pointed to by @c
  191. * from simultaneous access or modification.
  192. *
  193. * Return: 0 upon success; anything else upon failure.
  194. */
  195. int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
  196. unsigned long parent_rate)
  197. {
  198. unsigned long ratio;
  199. u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre;
  200. u32 best_f, f, post_divr_freq;
  201. u8 fbdiv, divq, best_r, r;
  202. int range;
  203. if (c->flags == 0) {
  204. WARN(1, "%s called with uninitialized PLL config", __func__);
  205. return -EINVAL;
  206. }
  207. /* Initialize rounding data if it hasn't been initialized already */
  208. if (parent_rate != c->parent_rate) {
  209. if (__wrpll_update_parent_rate(c, parent_rate)) {
  210. pr_err("%s: PLL input rate is out of range\n",
  211. __func__);
  212. return -ERANGE;
  213. }
  214. }
  215. c->flags &= ~WRPLL_FLAGS_RESET_MASK;
  216. /* Put the PLL into bypass if the user requests the parent clock rate */
  217. if (target_rate == parent_rate) {
  218. c->flags |= WRPLL_FLAGS_BYPASS_MASK;
  219. return 0;
  220. }
  221. c->flags &= ~WRPLL_FLAGS_BYPASS_MASK;
  222. /* Calculate the Q shift and target VCO rate */
  223. divq = __wrpll_calc_divq(target_rate, &target_vco_rate);
  224. if (!divq)
  225. return -1;
  226. c->divq = divq;
  227. /* Precalculate the pre-Q divider target ratio */
  228. ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate);
  229. fbdiv = __wrpll_calc_fbdiv(c);
  230. best_r = 0;
  231. best_f = 0;
  232. best_delta = MAX_VCO_FREQ;
  233. /*
  234. * Consider all values for R which land within
  235. * [MIN_POST_DIVR_FREQ, MAX_POST_DIVR_FREQ]; prefer smaller R
  236. */
  237. for (r = c->init_r; r <= c->max_r; ++r) {
  238. f_pre_div = ratio * r;
  239. f = (f_pre_div + (1 << ROUND_SHIFT)) >> ROUND_SHIFT;
  240. f >>= (fbdiv - 1);
  241. post_divr_freq = div_u64(parent_rate, r);
  242. vco_pre = fbdiv * post_divr_freq;
  243. vco = vco_pre * f;
  244. /* Ensure rounding didn't take us out of range */
  245. if (vco > target_vco_rate) {
  246. --f;
  247. vco = vco_pre * f;
  248. } else if (vco < MIN_VCO_FREQ) {
  249. ++f;
  250. vco = vco_pre * f;
  251. }
  252. delta = abs(target_rate - vco);
  253. if (delta < best_delta) {
  254. best_delta = delta;
  255. best_r = r;
  256. best_f = f;
  257. }
  258. }
  259. c->divr = best_r - 1;
  260. c->divf = best_f - 1;
  261. post_divr_freq = div_u64(parent_rate, best_r);
  262. /* Pick the best PLL jitter filter */
  263. range = __wrpll_calc_filter_range(post_divr_freq);
  264. if (range < 0)
  265. return range;
  266. c->range = range;
  267. return 0;
  268. }
  269. /**
  270. * wrpll_calc_output_rate() - calculate the PLL's target output rate
  271. * @c: ptr to a struct wrpll_cfg record to read from
  272. * @parent_rate: PLL refclk rate
  273. *
  274. * Given a pointer to the PLL's current input configuration @c and the
  275. * PLL's input reference clock rate @parent_rate (before the R
  276. * pre-divider), calculate the PLL's output clock rate (after the Q
  277. * post-divider).
  278. *
  279. * Context: Any context. Caller must protect the memory pointed to by @c
  280. * from simultaneous modification.
  281. *
  282. * Return: the PLL's output clock rate, in Hz. The return value from
  283. * this function is intended to be convenient to pass directly
  284. * to the Linux clock framework; thus there is no explicit
  285. * error return value.
  286. */
  287. unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
  288. unsigned long parent_rate)
  289. {
  290. u8 fbdiv;
  291. u64 n;
  292. if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
  293. WARN(1, "external feedback mode not yet supported");
  294. return ULONG_MAX;
  295. }
  296. fbdiv = __wrpll_calc_fbdiv(c);
  297. n = parent_rate * fbdiv * (c->divf + 1);
  298. n = div_u64(n, c->divr + 1);
  299. n >>= c->divq;
  300. return n;
  301. }
  302. /**
  303. * wrpll_calc_max_lock_us() - return the time for the PLL to lock
  304. * @c: ptr to a struct wrpll_cfg record to read from
  305. *
  306. * Return the minimum amount of time (in microseconds) that the caller
  307. * must wait after reprogramming the PLL to ensure that it is locked
  308. * to the input frequency and stable. This is likely to depend on the DIVR
  309. * value; this is under discussion with the manufacturer.
  310. *
  311. * Return: the minimum amount of time the caller must wait for the PLL
  312. * to lock (in microseconds)
  313. */
  314. unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c)
  315. {
  316. return MAX_LOCK_US;
  317. }