dwc_ahsata.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  4. * Terry Lv <r65388@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <ahci.h>
  8. #include <blk.h>
  9. #include <cpu_func.h>
  10. #include <dm.h>
  11. #include <dwc_ahsata.h>
  12. #include <fis.h>
  13. #include <libata.h>
  14. #include <log.h>
  15. #include <malloc.h>
  16. #include <memalign.h>
  17. #include <part.h>
  18. #include <sata.h>
  19. #include <asm/cache.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/mach-imx/sata.h>
  24. #include <linux/bitops.h>
  25. #include <linux/ctype.h>
  26. #include <linux/delay.h>
  27. #include <linux/errno.h>
  28. #include "dwc_ahsata_priv.h"
  29. struct sata_port_regs {
  30. u32 clb;
  31. u32 clbu;
  32. u32 fb;
  33. u32 fbu;
  34. u32 is;
  35. u32 ie;
  36. u32 cmd;
  37. u32 res1[1];
  38. u32 tfd;
  39. u32 sig;
  40. u32 ssts;
  41. u32 sctl;
  42. u32 serr;
  43. u32 sact;
  44. u32 ci;
  45. u32 sntf;
  46. u32 res2[1];
  47. u32 dmacr;
  48. u32 res3[1];
  49. u32 phycr;
  50. u32 physr;
  51. };
  52. struct sata_host_regs {
  53. u32 cap;
  54. u32 ghc;
  55. u32 is;
  56. u32 pi;
  57. u32 vs;
  58. u32 ccc_ctl;
  59. u32 ccc_ports;
  60. u32 res1[2];
  61. u32 cap2;
  62. u32 res2[30];
  63. u32 bistafr;
  64. u32 bistcr;
  65. u32 bistfctr;
  66. u32 bistsr;
  67. u32 bistdecr;
  68. u32 res3[2];
  69. u32 oobr;
  70. u32 res4[8];
  71. u32 timer1ms;
  72. u32 res5[1];
  73. u32 gparam1r;
  74. u32 gparam2r;
  75. u32 pparamr;
  76. u32 testr;
  77. u32 versionr;
  78. u32 idr;
  79. };
  80. #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
  81. #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
  82. #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
  83. static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
  84. {
  85. return base + 0x100 + (port * 0x80);
  86. }
  87. static int waiting_for_cmd_completed(u8 *offset,
  88. int timeout_msec,
  89. u32 sign)
  90. {
  91. int i;
  92. u32 status;
  93. for (i = 0;
  94. ((status = readl(offset)) & sign) && i < timeout_msec;
  95. ++i)
  96. mdelay(1);
  97. return (i < timeout_msec) ? 0 : -1;
  98. }
  99. static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
  100. {
  101. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  102. writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
  103. writel(0x02060b14, &host_mmio->oobr);
  104. return 0;
  105. }
  106. static int ahci_host_init(struct ahci_uc_priv *uc_priv)
  107. {
  108. u32 tmp, cap_save, num_ports;
  109. int i, j, timeout = 1000;
  110. struct sata_port_regs *port_mmio = NULL;
  111. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  112. int clk = mxc_get_clock(MXC_SATA_CLK);
  113. cap_save = readl(&host_mmio->cap);
  114. cap_save |= SATA_HOST_CAP_SSS;
  115. /* global controller reset */
  116. tmp = readl(&host_mmio->ghc);
  117. if ((tmp & SATA_HOST_GHC_HR) == 0)
  118. writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
  119. while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
  120. ;
  121. if (timeout <= 0) {
  122. debug("controller reset failed (0x%x)\n", tmp);
  123. return -1;
  124. }
  125. /* Set timer 1ms */
  126. writel(clk / 1000, &host_mmio->timer1ms);
  127. ahci_setup_oobr(uc_priv, 0);
  128. writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
  129. writel(cap_save, &host_mmio->cap);
  130. num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
  131. writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
  132. /*
  133. * Determine which Ports are implemented by the DWC_ahsata,
  134. * by reading the PI register. This bit map value aids the
  135. * software to determine how many Ports are available and
  136. * which Port registers need to be initialized.
  137. */
  138. uc_priv->cap = readl(&host_mmio->cap);
  139. uc_priv->port_map = readl(&host_mmio->pi);
  140. /* Determine how many command slots the HBA supports */
  141. uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
  142. debug("cap 0x%x port_map 0x%x n_ports %d\n",
  143. uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
  144. for (i = 0; i < uc_priv->n_ports; i++) {
  145. uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
  146. port_mmio = uc_priv->port[i].port_mmio;
  147. /* Ensure that the DWC_ahsata is in idle state */
  148. tmp = readl(&port_mmio->cmd);
  149. /*
  150. * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
  151. * are all cleared, the Port is in an idle state.
  152. */
  153. if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
  154. SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
  155. /*
  156. * System software places a Port into the idle state by
  157. * clearing P#CMD.ST and waiting for P#CMD.CR to return
  158. * 0 when read.
  159. */
  160. tmp &= ~SATA_PORT_CMD_ST;
  161. writel_with_flush(tmp, &port_mmio->cmd);
  162. /*
  163. * spec says 500 msecs for each bit, so
  164. * this is slightly incorrect.
  165. */
  166. mdelay(500);
  167. timeout = 1000;
  168. while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
  169. && --timeout)
  170. ;
  171. if (timeout <= 0) {
  172. debug("port reset failed (0x%x)\n", tmp);
  173. return -1;
  174. }
  175. }
  176. /* Spin-up device */
  177. tmp = readl(&port_mmio->cmd);
  178. writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
  179. /* Wait for spin-up to finish */
  180. timeout = 1000;
  181. while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
  182. && --timeout)
  183. ;
  184. if (timeout <= 0) {
  185. debug("Spin-Up can't finish!\n");
  186. return -1;
  187. }
  188. for (j = 0; j < 100; ++j) {
  189. mdelay(10);
  190. tmp = readl(&port_mmio->ssts);
  191. if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
  192. ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
  193. break;
  194. }
  195. /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
  196. timeout = 1000;
  197. while (!(readl(&port_mmio->serr) & SATA_PORT_SERR_DIAG_X)
  198. && --timeout)
  199. ;
  200. if (timeout <= 0) {
  201. debug("Can't find DIAG_X set!\n");
  202. return -1;
  203. }
  204. /*
  205. * For each implemented Port, clear the P#SERR
  206. * register, by writing ones to each implemented\
  207. * bit location.
  208. */
  209. tmp = readl(&port_mmio->serr);
  210. debug("P#SERR 0x%x\n",
  211. tmp);
  212. writel(tmp, &port_mmio->serr);
  213. /* Ack any pending irq events for this port */
  214. tmp = readl(&host_mmio->is);
  215. debug("IS 0x%x\n", tmp);
  216. if (tmp)
  217. writel(tmp, &host_mmio->is);
  218. writel(1 << i, &host_mmio->is);
  219. /* set irq mask (enables interrupts) */
  220. writel(DEF_PORT_IRQ, &port_mmio->ie);
  221. /* register linkup ports */
  222. tmp = readl(&port_mmio->ssts);
  223. debug("Port %d status: 0x%x\n", i, tmp);
  224. if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
  225. uc_priv->link_port_map |= (0x01 << i);
  226. }
  227. tmp = readl(&host_mmio->ghc);
  228. debug("GHC 0x%x\n", tmp);
  229. writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
  230. tmp = readl(&host_mmio->ghc);
  231. debug("GHC 0x%x\n", tmp);
  232. return 0;
  233. }
  234. static void ahci_print_info(struct ahci_uc_priv *uc_priv)
  235. {
  236. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  237. u32 vers, cap, impl, speed;
  238. const char *speed_s;
  239. const char *scc_s;
  240. vers = readl(&host_mmio->vs);
  241. cap = uc_priv->cap;
  242. impl = uc_priv->port_map;
  243. speed = (cap & SATA_HOST_CAP_ISS_MASK)
  244. >> SATA_HOST_CAP_ISS_OFFSET;
  245. if (speed == 1)
  246. speed_s = "1.5";
  247. else if (speed == 2)
  248. speed_s = "3";
  249. else
  250. speed_s = "?";
  251. scc_s = "SATA";
  252. printf("AHCI %02x%02x.%02x%02x "
  253. "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  254. (vers >> 24) & 0xff,
  255. (vers >> 16) & 0xff,
  256. (vers >> 8) & 0xff,
  257. vers & 0xff,
  258. ((cap >> 8) & 0x1f) + 1,
  259. (cap & 0x1f) + 1,
  260. speed_s,
  261. impl,
  262. scc_s);
  263. printf("flags: "
  264. "%s%s%s%s%s%s"
  265. "%s%s%s%s%s%s%s\n",
  266. cap & (1 << 31) ? "64bit " : "",
  267. cap & (1 << 30) ? "ncq " : "",
  268. cap & (1 << 28) ? "ilck " : "",
  269. cap & (1 << 27) ? "stag " : "",
  270. cap & (1 << 26) ? "pm " : "",
  271. cap & (1 << 25) ? "led " : "",
  272. cap & (1 << 24) ? "clo " : "",
  273. cap & (1 << 19) ? "nz " : "",
  274. cap & (1 << 18) ? "only " : "",
  275. cap & (1 << 17) ? "pmp " : "",
  276. cap & (1 << 15) ? "pio " : "",
  277. cap & (1 << 14) ? "slum " : "",
  278. cap & (1 << 13) ? "part " : "");
  279. }
  280. static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
  281. unsigned char *buf, int buf_len)
  282. {
  283. struct ahci_ioports *pp = &uc_priv->port[port];
  284. struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  285. u32 sg_count, max_bytes;
  286. int i;
  287. max_bytes = MAX_DATA_BYTES_PER_SG;
  288. sg_count = ((buf_len - 1) / max_bytes) + 1;
  289. if (sg_count > AHCI_MAX_SG) {
  290. printf("Error:Too much sg!\n");
  291. return -1;
  292. }
  293. for (i = 0; i < sg_count; i++) {
  294. ahci_sg->addr =
  295. cpu_to_le32((u32)buf + i * max_bytes);
  296. ahci_sg->addr_hi = 0;
  297. ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  298. (buf_len < max_bytes
  299. ? (buf_len - 1)
  300. : (max_bytes - 1)));
  301. ahci_sg++;
  302. buf_len -= max_bytes;
  303. }
  304. return sg_count;
  305. }
  306. static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
  307. {
  308. struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
  309. AHCI_CMD_SLOT_SZ * cmd_slot);
  310. memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
  311. cmd_hdr->opts = cpu_to_le32(opts);
  312. cmd_hdr->status = 0;
  313. pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
  314. #ifdef CONFIG_PHYS_64BIT
  315. pp->cmd_slot->tbl_addr_hi =
  316. cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
  317. #endif
  318. }
  319. #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
  320. static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
  321. struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
  322. s32 is_write)
  323. {
  324. struct ahci_ioports *pp = &uc_priv->port[port];
  325. struct sata_port_regs *port_mmio = pp->port_mmio;
  326. u32 opts;
  327. int sg_count = 0, cmd_slot = 0;
  328. cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
  329. if (32 == cmd_slot) {
  330. printf("Can't find empty command slot!\n");
  331. return 0;
  332. }
  333. /* Check xfer length */
  334. if (buf_len > MAX_BYTES_PER_TRANS) {
  335. printf("Max transfer length is %dB\n\r",
  336. MAX_BYTES_PER_TRANS);
  337. return 0;
  338. }
  339. memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
  340. if (buf && buf_len)
  341. sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
  342. opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
  343. if (is_write) {
  344. opts |= 0x40;
  345. flush_cache((ulong)buf, buf_len);
  346. }
  347. ahci_fill_cmd_slot(pp, cmd_slot, opts);
  348. flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
  349. writel_with_flush(1 << cmd_slot, &port_mmio->ci);
  350. if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
  351. 0x1 << cmd_slot)) {
  352. printf("timeout exit!\n");
  353. return -1;
  354. }
  355. invalidate_dcache_range((int)(pp->cmd_slot),
  356. (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
  357. debug("ahci_exec_ata_cmd: %d byte transferred.\n",
  358. pp->cmd_slot->status);
  359. if (!is_write)
  360. invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
  361. return buf_len;
  362. }
  363. static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
  364. {
  365. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  366. struct sata_fis_h2d *cfis = &h2d;
  367. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  368. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  369. cfis->pm_port_c = 1 << 7;
  370. cfis->command = ATA_CMD_SET_FEATURES;
  371. cfis->features = SETFEATURES_XFER;
  372. cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
  373. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
  374. }
  375. static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
  376. {
  377. struct ahci_ioports *pp = &uc_priv->port[port];
  378. struct sata_port_regs *port_mmio = pp->port_mmio;
  379. u32 port_status;
  380. u32 mem;
  381. int timeout = 10000000;
  382. debug("Enter start port: %d\n", port);
  383. port_status = readl(&port_mmio->ssts);
  384. debug("Port %d status: %x\n", port, port_status);
  385. if ((port_status & 0xf) != 0x03) {
  386. printf("No Link on this port!\n");
  387. return -1;
  388. }
  389. mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
  390. if (!mem) {
  391. printf("No mem for table!\n");
  392. return -ENOMEM;
  393. }
  394. mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
  395. memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  396. /*
  397. * First item in chunk of DMA memory: 32-slot command table,
  398. * 32 bytes each in size
  399. */
  400. pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
  401. debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
  402. mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
  403. /*
  404. * Second item: Received-FIS area, 256-Byte aligned
  405. */
  406. pp->rx_fis = mem;
  407. mem += AHCI_RX_FIS_SZ;
  408. /*
  409. * Third item: data area for storing a single command
  410. * and its scatter-gather table
  411. */
  412. pp->cmd_tbl = mem;
  413. debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
  414. mem += AHCI_CMD_TBL_HDR;
  415. writel_with_flush(0x00004444, &port_mmio->dmacr);
  416. pp->cmd_tbl_sg = (struct ahci_sg *)mem;
  417. writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
  418. writel_with_flush(pp->rx_fis, &port_mmio->fb);
  419. /* Enable FRE */
  420. writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
  421. &port_mmio->cmd);
  422. /* Wait device ready */
  423. while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
  424. SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
  425. && --timeout)
  426. ;
  427. if (timeout <= 0) {
  428. debug("Device not ready for BSY, DRQ and"
  429. "ERR in TFD!\n");
  430. return -1;
  431. }
  432. writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  433. PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  434. PORT_CMD_START, &port_mmio->cmd);
  435. debug("Exit start port %d\n", port);
  436. return 0;
  437. }
  438. static void dwc_ahsata_print_info(struct blk_desc *pdev)
  439. {
  440. printf("SATA Device Info:\n\r");
  441. printf("S/N: %s\n\rProduct model number: %s\n\r"
  442. "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r",
  443. pdev->product, pdev->vendor, pdev->revision, pdev->lba);
  444. }
  445. static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
  446. {
  447. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  448. struct sata_fis_h2d *cfis = &h2d;
  449. u8 port = uc_priv->hard_port_no;
  450. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  451. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  452. cfis->pm_port_c = 0x80; /* is command */
  453. cfis->command = ATA_CMD_ID_ATA;
  454. ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
  455. READ_CMD);
  456. ata_swap_buf_le16(id, ATA_ID_WORDS);
  457. }
  458. static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
  459. {
  460. uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
  461. uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
  462. debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
  463. }
  464. static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
  465. u32 blkcnt, u8 *buffer, int is_write)
  466. {
  467. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  468. struct sata_fis_h2d *cfis = &h2d;
  469. u8 port = uc_priv->hard_port_no;
  470. u32 block;
  471. block = start;
  472. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  473. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  474. cfis->pm_port_c = 0x80; /* is command */
  475. cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  476. cfis->device = ATA_LBA;
  477. cfis->device |= (block >> 24) & 0xf;
  478. cfis->lba_high = (block >> 16) & 0xff;
  479. cfis->lba_mid = (block >> 8) & 0xff;
  480. cfis->lba_low = block & 0xff;
  481. cfis->sector_count = (u8)(blkcnt & 0xff);
  482. if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
  483. ATA_SECT_SIZE * blkcnt, is_write) > 0)
  484. return blkcnt;
  485. else
  486. return 0;
  487. }
  488. static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
  489. {
  490. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  491. struct sata_fis_h2d *cfis = &h2d;
  492. u8 port = uc_priv->hard_port_no;
  493. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  494. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  495. cfis->pm_port_c = 0x80; /* is command */
  496. cfis->command = ATA_CMD_FLUSH;
  497. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
  498. }
  499. static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
  500. lbaint_t blkcnt, u8 *buffer, int is_write)
  501. {
  502. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  503. struct sata_fis_h2d *cfis = &h2d;
  504. u8 port = uc_priv->hard_port_no;
  505. u64 block;
  506. block = (u64)start;
  507. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  508. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  509. cfis->pm_port_c = 0x80; /* is command */
  510. cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
  511. : ATA_CMD_READ_EXT;
  512. cfis->lba_high_exp = (block >> 40) & 0xff;
  513. cfis->lba_mid_exp = (block >> 32) & 0xff;
  514. cfis->lba_low_exp = (block >> 24) & 0xff;
  515. cfis->lba_high = (block >> 16) & 0xff;
  516. cfis->lba_mid = (block >> 8) & 0xff;
  517. cfis->lba_low = block & 0xff;
  518. cfis->device = ATA_LBA;
  519. cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
  520. cfis->sector_count = blkcnt & 0xff;
  521. if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
  522. ATA_SECT_SIZE * blkcnt, is_write) > 0)
  523. return blkcnt;
  524. else
  525. return 0;
  526. }
  527. static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
  528. {
  529. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  530. struct sata_fis_h2d *cfis = &h2d;
  531. u8 port = uc_priv->hard_port_no;
  532. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  533. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  534. cfis->pm_port_c = 0x80; /* is command */
  535. cfis->command = ATA_CMD_FLUSH_EXT;
  536. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
  537. }
  538. static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
  539. {
  540. if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
  541. uc_priv->flags |= SATA_FLAG_WCACHE;
  542. if (ata_id_has_flush(id))
  543. uc_priv->flags |= SATA_FLAG_FLUSH;
  544. if (ata_id_has_flush_ext(id))
  545. uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
  546. }
  547. static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
  548. lbaint_t blkcnt, const void *buffer,
  549. int is_write)
  550. {
  551. u32 start, blks;
  552. u8 *addr;
  553. int max_blks;
  554. start = blknr;
  555. blks = blkcnt;
  556. addr = (u8 *)buffer;
  557. max_blks = ATA_MAX_SECTORS_LBA48;
  558. do {
  559. if (blks > max_blks) {
  560. if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
  561. max_blks, addr,
  562. is_write))
  563. return 0;
  564. start += max_blks;
  565. blks -= max_blks;
  566. addr += ATA_SECT_SIZE * max_blks;
  567. } else {
  568. if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
  569. addr, is_write))
  570. return 0;
  571. start += blks;
  572. blks = 0;
  573. addr += ATA_SECT_SIZE * blks;
  574. }
  575. } while (blks != 0);
  576. return blkcnt;
  577. }
  578. static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
  579. lbaint_t blkcnt, const void *buffer,
  580. int is_write)
  581. {
  582. u32 start, blks;
  583. u8 *addr;
  584. int max_blks;
  585. start = blknr;
  586. blks = blkcnt;
  587. addr = (u8 *)buffer;
  588. max_blks = ATA_MAX_SECTORS;
  589. do {
  590. if (blks > max_blks) {
  591. if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
  592. max_blks, addr,
  593. is_write))
  594. return 0;
  595. start += max_blks;
  596. blks -= max_blks;
  597. addr += ATA_SECT_SIZE * max_blks;
  598. } else {
  599. if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
  600. addr, is_write))
  601. return 0;
  602. start += blks;
  603. blks = 0;
  604. addr += ATA_SECT_SIZE * blks;
  605. }
  606. } while (blks != 0);
  607. return blkcnt;
  608. }
  609. static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
  610. {
  611. u32 linkmap;
  612. int i;
  613. linkmap = uc_priv->link_port_map;
  614. if (0 == linkmap) {
  615. printf("No port device detected!\n");
  616. return -ENXIO;
  617. }
  618. for (i = 0; i < uc_priv->n_ports; i++) {
  619. if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
  620. if (ahci_port_start(uc_priv, (u8)i)) {
  621. printf("Can not start port %d\n", i);
  622. return 1;
  623. }
  624. uc_priv->hard_port_no = i;
  625. break;
  626. }
  627. }
  628. return 0;
  629. }
  630. static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
  631. struct blk_desc *pdev)
  632. {
  633. u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
  634. u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
  635. u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
  636. u8 port = uc_priv->hard_port_no;
  637. ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
  638. /* Identify device to get information */
  639. dwc_ahsata_identify(uc_priv, id);
  640. /* Serial number */
  641. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  642. memcpy(pdev->product, serial, sizeof(serial));
  643. /* Firmware version */
  644. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  645. memcpy(pdev->revision, firmware, sizeof(firmware));
  646. /* Product model */
  647. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  648. memcpy(pdev->vendor, product, sizeof(product));
  649. /* Total sectors */
  650. pdev->lba = ata_id_n_sectors(id);
  651. pdev->type = DEV_TYPE_HARDDISK;
  652. pdev->blksz = ATA_SECT_SIZE;
  653. pdev->lun = 0;
  654. /* Check if support LBA48 */
  655. if (ata_id_has_lba48(id)) {
  656. pdev->lba48 = 1;
  657. debug("Device support LBA48\n\r");
  658. }
  659. /* Get the NCQ queue depth from device */
  660. uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
  661. uc_priv->flags |= ata_id_queue_depth(id);
  662. /* Get the xfer mode from device */
  663. dwc_ahsata_xfer_mode(uc_priv, id);
  664. /* Get the write cache status from device */
  665. dwc_ahsata_init_wcache(uc_priv, id);
  666. /* Set the xfer mode to highest speed */
  667. ahci_set_feature(uc_priv, port);
  668. dwc_ahsata_print_info(pdev);
  669. return 0;
  670. }
  671. /*
  672. * SATA interface between low level driver and command layer
  673. */
  674. static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
  675. struct blk_desc *desc, ulong blknr,
  676. lbaint_t blkcnt, void *buffer)
  677. {
  678. u32 rc;
  679. if (desc->lba48)
  680. rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
  681. READ_CMD);
  682. else
  683. rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
  684. READ_CMD);
  685. return rc;
  686. }
  687. static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
  688. struct blk_desc *desc, ulong blknr,
  689. lbaint_t blkcnt, const void *buffer)
  690. {
  691. u32 rc;
  692. u32 flags = uc_priv->flags;
  693. if (desc->lba48) {
  694. rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
  695. WRITE_CMD);
  696. if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
  697. dwc_ahsata_flush_cache_ext(uc_priv);
  698. } else {
  699. rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
  700. WRITE_CMD);
  701. if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
  702. dwc_ahsata_flush_cache(uc_priv);
  703. }
  704. return rc;
  705. }
  706. #if !CONFIG_IS_ENABLED(AHCI)
  707. static int ahci_init_one(int pdev)
  708. {
  709. int rc;
  710. struct ahci_uc_priv *uc_priv = NULL;
  711. uc_priv = malloc(sizeof(struct ahci_uc_priv));
  712. if (!uc_priv)
  713. return -ENOMEM;
  714. memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
  715. uc_priv->dev = pdev;
  716. uc_priv->host_flags = ATA_FLAG_SATA
  717. | ATA_FLAG_NO_LEGACY
  718. | ATA_FLAG_MMIO
  719. | ATA_FLAG_PIO_DMA
  720. | ATA_FLAG_NO_ATAPI;
  721. uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
  722. /* initialize adapter */
  723. rc = ahci_host_init(uc_priv);
  724. if (rc)
  725. goto err_out;
  726. ahci_print_info(uc_priv);
  727. /* Save the uc_private struct to block device struct */
  728. sata_dev_desc[pdev].priv = uc_priv;
  729. return 0;
  730. err_out:
  731. if (uc_priv)
  732. free(uc_priv);
  733. return rc;
  734. }
  735. int init_sata(int dev)
  736. {
  737. struct ahci_uc_priv *uc_priv = NULL;
  738. #if defined(CONFIG_MX6)
  739. if (!is_mx6dq() && !is_mx6dqp())
  740. return 1;
  741. #endif
  742. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  743. printf("The sata index %d is out of ranges\n\r", dev);
  744. return -1;
  745. }
  746. ahci_init_one(dev);
  747. uc_priv = sata_dev_desc[dev].priv;
  748. return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
  749. }
  750. int reset_sata(int dev)
  751. {
  752. struct ahci_uc_priv *uc_priv;
  753. struct sata_host_regs *host_mmio;
  754. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  755. printf("The sata index %d is out of ranges\n\r", dev);
  756. return -1;
  757. }
  758. uc_priv = sata_dev_desc[dev].priv;
  759. if (NULL == uc_priv)
  760. /* not initialized, so nothing to reset */
  761. return 0;
  762. host_mmio = uc_priv->mmio_base;
  763. setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
  764. while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
  765. udelay(100);
  766. free(uc_priv);
  767. memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc));
  768. return 0;
  769. }
  770. int sata_port_status(int dev, int port)
  771. {
  772. struct sata_port_regs *port_mmio;
  773. struct ahci_uc_priv *uc_priv = NULL;
  774. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
  775. return -EINVAL;
  776. if (sata_dev_desc[dev].priv == NULL)
  777. return -ENODEV;
  778. uc_priv = sata_dev_desc[dev].priv;
  779. port_mmio = uc_priv->port[port].port_mmio;
  780. return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
  781. }
  782. /*
  783. * SATA interface between low level driver and command layer
  784. */
  785. ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
  786. {
  787. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  788. return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
  789. buffer);
  790. }
  791. ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
  792. {
  793. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  794. return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
  795. buffer);
  796. }
  797. int scan_sata(int dev)
  798. {
  799. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  800. struct blk_desc *pdev = &sata_dev_desc[dev];
  801. return dwc_ahsata_scan_common(uc_priv, pdev);
  802. }
  803. #endif /* CONFIG_IS_ENABLED(AHCI) */
  804. #if CONFIG_IS_ENABLED(AHCI)
  805. int dwc_ahsata_port_status(struct udevice *dev, int port)
  806. {
  807. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  808. struct sata_port_regs *port_mmio;
  809. port_mmio = uc_priv->port[port].port_mmio;
  810. return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
  811. }
  812. int dwc_ahsata_bus_reset(struct udevice *dev)
  813. {
  814. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  815. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  816. setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
  817. while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
  818. udelay(100);
  819. return 0;
  820. }
  821. int dwc_ahsata_scan(struct udevice *dev)
  822. {
  823. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  824. struct blk_desc *desc;
  825. struct udevice *blk;
  826. int ret;
  827. /*
  828. * Create only one block device and do detection
  829. * to make sure that there won't be a lot of
  830. * block devices created
  831. */
  832. device_find_first_child(dev, &blk);
  833. if (!blk) {
  834. ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
  835. IF_TYPE_SATA, -1, 512, 0, &blk);
  836. if (ret) {
  837. debug("Can't create device\n");
  838. return ret;
  839. }
  840. }
  841. desc = dev_get_uclass_platdata(blk);
  842. ret = dwc_ahsata_scan_common(uc_priv, desc);
  843. if (ret) {
  844. debug("%s: Failed to scan bus\n", __func__);
  845. return ret;
  846. }
  847. return 0;
  848. }
  849. int dwc_ahsata_probe(struct udevice *dev)
  850. {
  851. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  852. int ret;
  853. #if defined(CONFIG_MX6)
  854. setup_sata();
  855. #endif
  856. uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  857. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
  858. uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
  859. /* initialize adapter */
  860. ret = ahci_host_init(uc_priv);
  861. if (ret)
  862. return ret;
  863. ahci_print_info(uc_priv);
  864. return dwc_ahci_start_ports(uc_priv);
  865. }
  866. static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
  867. lbaint_t blkcnt, void *buffer)
  868. {
  869. struct blk_desc *desc = dev_get_uclass_platdata(blk);
  870. struct udevice *dev = dev_get_parent(blk);
  871. struct ahci_uc_priv *uc_priv;
  872. uc_priv = dev_get_uclass_priv(dev);
  873. return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
  874. }
  875. static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
  876. lbaint_t blkcnt, const void *buffer)
  877. {
  878. struct blk_desc *desc = dev_get_uclass_platdata(blk);
  879. struct udevice *dev = dev_get_parent(blk);
  880. struct ahci_uc_priv *uc_priv;
  881. uc_priv = dev_get_uclass_priv(dev);
  882. return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
  883. }
  884. static const struct blk_ops dwc_ahsata_blk_ops = {
  885. .read = dwc_ahsata_read,
  886. .write = dwc_ahsata_write,
  887. };
  888. U_BOOT_DRIVER(dwc_ahsata_blk) = {
  889. .name = "dwc_ahsata_blk",
  890. .id = UCLASS_BLK,
  891. .ops = &dwc_ahsata_blk_ops,
  892. };
  893. #if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
  894. struct ahci_ops dwc_ahsata_ahci_ops = {
  895. .port_status = dwc_ahsata_port_status,
  896. .reset = dwc_ahsata_bus_reset,
  897. .scan = dwc_ahsata_scan,
  898. };
  899. static const struct udevice_id dwc_ahsata_ahci_ids[] = {
  900. { .compatible = "fsl,imx6q-ahci" },
  901. { }
  902. };
  903. U_BOOT_DRIVER(dwc_ahsata_ahci) = {
  904. .name = "dwc_ahsata_ahci",
  905. .id = UCLASS_AHCI,
  906. .of_match = dwc_ahsata_ahci_ids,
  907. .ops = &dwc_ahsata_ahci_ops,
  908. .probe = dwc_ahsata_probe,
  909. };
  910. #endif
  911. #endif