stm32-adc-core.c 5.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
  5. *
  6. * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc-core.c.
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <asm/io.h>
  11. #include <dm/device_compat.h>
  12. #include <linux/bitops.h>
  13. #include <power/regulator.h>
  14. #include "stm32-adc-core.h"
  15. /* STM32H7 - common registers for all ADC instances */
  16. #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
  17. /* STM32H7_ADC_CCR - bit fields */
  18. #define STM32H7_PRESC_SHIFT 18
  19. #define STM32H7_PRESC_MASK GENMASK(21, 18)
  20. #define STM32H7_CKMODE_SHIFT 16
  21. #define STM32H7_CKMODE_MASK GENMASK(17, 16)
  22. /* STM32 H7 maximum analog clock rate (from datasheet) */
  23. #define STM32H7_ADC_MAX_CLK_RATE 36000000
  24. /**
  25. * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
  26. * @ckmode: ADC clock mode, Async or sync with prescaler.
  27. * @presc: prescaler bitfield for async clock mode
  28. * @div: prescaler division ratio
  29. */
  30. struct stm32h7_adc_ck_spec {
  31. u32 ckmode;
  32. u32 presc;
  33. int div;
  34. };
  35. static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
  36. /* 00: CK_ADC[1..3]: Asynchronous clock modes */
  37. { 0, 0, 1 },
  38. { 0, 1, 2 },
  39. { 0, 2, 4 },
  40. { 0, 3, 6 },
  41. { 0, 4, 8 },
  42. { 0, 5, 10 },
  43. { 0, 6, 12 },
  44. { 0, 7, 16 },
  45. { 0, 8, 32 },
  46. { 0, 9, 64 },
  47. { 0, 10, 128 },
  48. { 0, 11, 256 },
  49. /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
  50. { 1, 0, 1 },
  51. { 2, 0, 2 },
  52. { 3, 0, 4 },
  53. };
  54. static int stm32h7_adc_clk_sel(struct udevice *dev,
  55. struct stm32_adc_common *common)
  56. {
  57. u32 ckmode, presc;
  58. unsigned long rate;
  59. unsigned int i;
  60. int div;
  61. /* stm32h7 bus clock is common for all ADC instances (mandatory) */
  62. if (!clk_valid(&common->bclk)) {
  63. dev_err(dev, "No bclk clock found\n");
  64. return -ENOENT;
  65. }
  66. /*
  67. * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
  68. * So, choice is to have bus clock mandatory and adc clock optional.
  69. * If optional 'adc' clock has been found, then try to use it first.
  70. */
  71. if (clk_valid(&common->aclk)) {
  72. /*
  73. * Asynchronous clock modes (e.g. ckmode == 0)
  74. * From spec: PLL output musn't exceed max rate
  75. */
  76. rate = clk_get_rate(&common->aclk);
  77. if (!rate) {
  78. dev_err(dev, "Invalid aclk rate: 0\n");
  79. return -EINVAL;
  80. }
  81. for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
  82. ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
  83. presc = stm32h7_adc_ckmodes_spec[i].presc;
  84. div = stm32h7_adc_ckmodes_spec[i].div;
  85. if (ckmode)
  86. continue;
  87. if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
  88. goto out;
  89. }
  90. }
  91. /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
  92. rate = clk_get_rate(&common->bclk);
  93. if (!rate) {
  94. dev_err(dev, "Invalid bus clock rate: 0\n");
  95. return -EINVAL;
  96. }
  97. for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
  98. ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
  99. presc = stm32h7_adc_ckmodes_spec[i].presc;
  100. div = stm32h7_adc_ckmodes_spec[i].div;
  101. if (!ckmode)
  102. continue;
  103. if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
  104. goto out;
  105. }
  106. dev_err(dev, "clk selection failed\n");
  107. return -EINVAL;
  108. out:
  109. /* rate used later by each ADC instance to control BOOST mode */
  110. common->rate = rate / div;
  111. /* Set common clock mode and prescaler */
  112. clrsetbits_le32(common->base + STM32H7_ADC_CCR,
  113. STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK,
  114. ckmode << STM32H7_CKMODE_SHIFT |
  115. presc << STM32H7_PRESC_SHIFT);
  116. dev_dbg(dev, "Using %s clock/%d source at %ld kHz\n",
  117. ckmode ? "bus" : "adc", div, common->rate / 1000);
  118. return 0;
  119. }
  120. static int stm32_adc_core_probe(struct udevice *dev)
  121. {
  122. struct stm32_adc_common *common = dev_get_priv(dev);
  123. int ret;
  124. common->base = dev_read_addr_ptr(dev);
  125. if (!common->base) {
  126. dev_err(dev, "can't get address\n");
  127. return -ENOENT;
  128. }
  129. ret = device_get_supply_regulator(dev, "vref-supply", &common->vref);
  130. if (ret) {
  131. dev_err(dev, "can't get vref-supply: %d\n", ret);
  132. return ret;
  133. }
  134. ret = regulator_get_value(common->vref);
  135. if (ret < 0) {
  136. dev_err(dev, "can't get vref-supply value: %d\n", ret);
  137. return ret;
  138. }
  139. common->vref_uv = ret;
  140. ret = clk_get_by_name(dev, "adc", &common->aclk);
  141. if (!ret) {
  142. ret = clk_enable(&common->aclk);
  143. if (ret) {
  144. dev_err(dev, "Can't enable aclk: %d\n", ret);
  145. return ret;
  146. }
  147. }
  148. ret = clk_get_by_name(dev, "bus", &common->bclk);
  149. if (!ret) {
  150. ret = clk_enable(&common->bclk);
  151. if (ret) {
  152. dev_err(dev, "Can't enable bclk: %d\n", ret);
  153. goto err_aclk_disable;
  154. }
  155. }
  156. ret = stm32h7_adc_clk_sel(dev, common);
  157. if (ret)
  158. goto err_bclk_disable;
  159. return ret;
  160. err_bclk_disable:
  161. if (clk_valid(&common->bclk))
  162. clk_disable(&common->bclk);
  163. err_aclk_disable:
  164. if (clk_valid(&common->aclk))
  165. clk_disable(&common->aclk);
  166. return ret;
  167. }
  168. static const struct udevice_id stm32_adc_core_ids[] = {
  169. { .compatible = "st,stm32h7-adc-core" },
  170. { .compatible = "st,stm32mp1-adc-core" },
  171. {}
  172. };
  173. U_BOOT_DRIVER(stm32_adc_core) = {
  174. .name = "stm32-adc-core",
  175. .id = UCLASS_SIMPLE_BUS,
  176. .of_match = stm32_adc_core_ids,
  177. .probe = stm32_adc_core_probe,
  178. .priv_auto_alloc_size = sizeof(struct stm32_adc_common),
  179. };