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- SiFive PWM controller
- Unlike most other PWM controllers, the SiFive PWM controller currently only
- supports one period for all channels in the PWM. All PWMs need to run at
- the same period. The period also has significant restrictions on the values
- it can achieve, which the driver rounds to the nearest achievable period.
- PWM RTL that corresponds to the IP block version numbers can be found
- here:
- https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
- Required properties:
- - compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
- Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
- PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
- SiFive PWM v0 IP block with no chip integration tweaks.
- - reg: physical base address and length of the controller's registers
- - clocks: Should contain a clock identifier for the PWM's parent clock.
- - #pwm-cells: Should be 3.
- - interrupts: one interrupt per PWM channel
- Examples:
- pwm: pwm@10020000 {
- compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
- reg = <0x0 0x10020000 0x0 0x1000>;
- clocks = <&tlclk>;
- interrupt-parent = <&plic>;
- interrupts = <42 43 44 45>;
- #pwm-cells = <3>;
- };
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