pwm-sifive.txt 1.2 KB

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  1. SiFive PWM controller
  2. Unlike most other PWM controllers, the SiFive PWM controller currently only
  3. supports one period for all channels in the PWM. All PWMs need to run at
  4. the same period. The period also has significant restrictions on the values
  5. it can achieve, which the driver rounds to the nearest achievable period.
  6. PWM RTL that corresponds to the IP block version numbers can be found
  7. here:
  8. https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
  9. Required properties:
  10. - compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
  11. Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
  12. PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
  13. SiFive PWM v0 IP block with no chip integration tweaks.
  14. - reg: physical base address and length of the controller's registers
  15. - clocks: Should contain a clock identifier for the PWM's parent clock.
  16. - #pwm-cells: Should be 3.
  17. - interrupts: one interrupt per PWM channel
  18. Examples:
  19. pwm: pwm@10020000 {
  20. compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
  21. reg = <0x0 0x10020000 0x0 0x1000>;
  22. clocks = <&tlclk>;
  23. interrupt-parent = <&plic>;
  24. interrupts = <42 43 44 45>;
  25. #pwm-cells = <3>;
  26. };