board.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2018 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <env.h>
  9. #include <fdtdec.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <time.h>
  14. #include <asm/cache.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <dm/device.h>
  19. #include <dm/uclass.h>
  20. #include <versalpl.h>
  21. #include "../common/board.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #if defined(CONFIG_FPGA_VERSALPL)
  24. static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  25. #endif
  26. int board_init(void)
  27. {
  28. printf("EL Level:\tEL%d\n", current_el());
  29. #if defined(CONFIG_FPGA_VERSALPL)
  30. fpga_init();
  31. fpga_add(fpga_xilinx, &versalpl);
  32. #endif
  33. return 0;
  34. }
  35. int board_early_init_r(void)
  36. {
  37. u32 val;
  38. if (current_el() != 3)
  39. return 0;
  40. debug("iou_switch ctrl div0 %x\n",
  41. readl(&crlapb_base->iou_switch_ctrl));
  42. writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  43. (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  44. &crlapb_base->iou_switch_ctrl);
  45. /* Global timer init - Program time stamp reference clk */
  46. val = readl(&crlapb_base->timestamp_ref_ctrl);
  47. val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  48. writel(val, &crlapb_base->timestamp_ref_ctrl);
  49. debug("ref ctrl 0x%x\n",
  50. readl(&crlapb_base->timestamp_ref_ctrl));
  51. /* Clear reset of timestamp reg */
  52. writel(0, &crlapb_base->rst_timestamp);
  53. /*
  54. * Program freq register in System counter and
  55. * enable system counter.
  56. */
  57. writel(COUNTER_FREQUENCY,
  58. &iou_scntr_secure->base_frequency_id_register);
  59. debug("counter val 0x%x\n",
  60. readl(&iou_scntr_secure->base_frequency_id_register));
  61. writel(IOU_SCNTRS_CONTROL_EN,
  62. &iou_scntr_secure->counter_control_register);
  63. debug("scntrs control 0x%x\n",
  64. readl(&iou_scntr_secure->counter_control_register));
  65. debug("timer 0x%llx\n", get_ticks());
  66. debug("timer 0x%llx\n", get_ticks());
  67. return 0;
  68. }
  69. static u8 versal_get_bootmode(void)
  70. {
  71. u8 bootmode;
  72. u32 reg = 0;
  73. reg = readl(&crp_base->boot_mode_usr);
  74. if (reg >> BOOT_MODE_ALT_SHIFT)
  75. reg >>= BOOT_MODE_ALT_SHIFT;
  76. bootmode = reg & BOOT_MODES_MASK;
  77. return bootmode;
  78. }
  79. int board_late_init(void)
  80. {
  81. u8 bootmode;
  82. struct udevice *dev;
  83. int bootseq = -1;
  84. int bootseq_len = 0;
  85. int env_targets_len = 0;
  86. const char *mode;
  87. char *new_targets;
  88. char *env_targets;
  89. if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  90. debug("Saved variables - Skipping\n");
  91. return 0;
  92. }
  93. if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
  94. return 0;
  95. bootmode = versal_get_bootmode();
  96. puts("Bootmode: ");
  97. switch (bootmode) {
  98. case USB_MODE:
  99. puts("USB_MODE\n");
  100. mode = "dfu_usb";
  101. break;
  102. case JTAG_MODE:
  103. puts("JTAG_MODE\n");
  104. mode = "jtag pxe dhcp";
  105. break;
  106. case QSPI_MODE_24BIT:
  107. puts("QSPI_MODE_24\n");
  108. mode = "xspi0";
  109. break;
  110. case QSPI_MODE_32BIT:
  111. puts("QSPI_MODE_32\n");
  112. mode = "xspi0";
  113. break;
  114. case OSPI_MODE:
  115. puts("OSPI_MODE\n");
  116. mode = "xspi0";
  117. break;
  118. case EMMC_MODE:
  119. puts("EMMC_MODE\n");
  120. if (uclass_get_device_by_name(UCLASS_MMC,
  121. "sdhci@f1050000", &dev)) {
  122. puts("Boot from EMMC but without SD1 enabled!\n");
  123. return -1;
  124. }
  125. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  126. mode = "mmc";
  127. bootseq = dev->seq;
  128. break;
  129. case SD_MODE:
  130. puts("SD_MODE\n");
  131. if (uclass_get_device_by_name(UCLASS_MMC,
  132. "sdhci@f1040000", &dev)) {
  133. puts("Boot from SD0 but without SD0 enabled!\n");
  134. return -1;
  135. }
  136. debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
  137. mode = "mmc";
  138. bootseq = dev->seq;
  139. break;
  140. case SD1_LSHFT_MODE:
  141. puts("LVL_SHFT_");
  142. /* fall through */
  143. case SD_MODE1:
  144. puts("SD_MODE1\n");
  145. if (uclass_get_device_by_name(UCLASS_MMC,
  146. "sdhci@f1050000", &dev)) {
  147. puts("Boot from SD1 but without SD1 enabled!\n");
  148. return -1;
  149. }
  150. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  151. mode = "mmc";
  152. bootseq = dev->seq;
  153. break;
  154. default:
  155. mode = "";
  156. printf("Invalid Boot Mode:0x%x\n", bootmode);
  157. break;
  158. }
  159. if (bootseq >= 0) {
  160. bootseq_len = snprintf(NULL, 0, "%i", bootseq);
  161. debug("Bootseq len: %x\n", bootseq_len);
  162. }
  163. /*
  164. * One terminating char + one byte for space between mode
  165. * and default boot_targets
  166. */
  167. env_targets = env_get("boot_targets");
  168. if (env_targets)
  169. env_targets_len = strlen(env_targets);
  170. new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
  171. bootseq_len);
  172. if (!new_targets)
  173. return -ENOMEM;
  174. if (bootseq >= 0)
  175. sprintf(new_targets, "%s%x %s", mode, bootseq,
  176. env_targets ? env_targets : "");
  177. else
  178. sprintf(new_targets, "%s %s", mode,
  179. env_targets ? env_targets : "");
  180. env_set("boot_targets", new_targets);
  181. return board_late_init_xilinx();
  182. }
  183. int dram_init_banksize(void)
  184. {
  185. int ret;
  186. ret = fdtdec_setup_memory_banksize();
  187. if (ret)
  188. return ret;
  189. mem_map_fill();
  190. return 0;
  191. }
  192. int dram_init(void)
  193. {
  194. if (fdtdec_setup_mem_size_base_lowest() != 0)
  195. return -EINVAL;
  196. return 0;
  197. }
  198. void reset_cpu(ulong addr)
  199. {
  200. }