ddr.c 8.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008 Extreme Engineering Solutions, Inc.
  4. * Copyright 2008 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <log.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <fsl_ddr_dimm_params.h>
  11. void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
  12. {
  13. i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
  14. sizeof(ddr2_spd_eeprom_t));
  15. }
  16. /*
  17. * There are four board-specific SDRAM timing parameters which must be
  18. * calculated based on the particular PCB artwork. These are:
  19. * 1.) CPO (Read Capture Delay)
  20. * - TIMING_CFG_2 register
  21. * Source: Calculation based on board trace lengths and
  22. * chip-specific internal delays.
  23. * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
  24. * - TIMING_CFG_2 register
  25. * Source: Calculation based on board trace lengths.
  26. * Unless clock and DQ lanes are very different
  27. * lengths (>2"), this should be set to the nominal value
  28. * of 1/2 clock delay.
  29. * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
  30. * - DDR_SDRAM_CLK_CNTL register
  31. * Source: Signal Integrity Simulations
  32. * 4.) 2T Timing on Addr/Ctl
  33. * - TIMING_CFG_2 register
  34. * Source: Signal Integrity Simulations
  35. * Usually only needed with heavy load/very high speed (>DDR2-800)
  36. *
  37. * ====== XPedite5370 DDR2-600 read delay calculations ======
  38. *
  39. * See Freescale's App Note AN2583 as refrence. This document also
  40. * contains the chip-specific delays for 8548E, 8572, etc.
  41. *
  42. * For MPC8572E
  43. * Minimum chip delay (Ch 0): 1.372ns
  44. * Maximum chip delay (Ch 0): 2.914ns
  45. * Minimum chip delay (Ch 1): 1.220ns
  46. * Maximum chip delay (Ch 1): 2.595ns
  47. *
  48. * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
  49. *
  50. * Minimum delay calc (Ch 0):
  51. * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
  52. * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
  53. * = 3808ps
  54. * = 3.808ns
  55. *
  56. * Maximum delay calc (Ch 0):
  57. * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
  58. * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps
  59. * = 6240ps
  60. * = 6.240ns
  61. *
  62. * Minimum delay calc (Ch 1):
  63. * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
  64. * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
  65. * = 3288ps
  66. * = 3.288ns
  67. *
  68. * Maximum delay calc (Ch 1):
  69. * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
  70. * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps
  71. * = 5536ps
  72. * = 5.536ns
  73. *
  74. * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
  75. * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
  76. * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
  77. * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
  78. *
  79. *
  80. * ====== XPedite5370 DDR2-800 read delay calculations ======
  81. *
  82. * See Freescale's App Note AN2583 as refrence. This document also
  83. * contains the chip-specific delays for 8548E, 8572, etc.
  84. *
  85. * For MPC8572E
  86. * Minimum chip delay (Ch 0): 1.372ns
  87. * Maximum chip delay (Ch 0): 2.914ns
  88. * Minimum chip delay (Ch 1): 1.220ns
  89. * Maximum chip delay (Ch 1): 2.595ns
  90. *
  91. * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
  92. *
  93. * Minimum delay calc (Ch 0):
  94. * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
  95. * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
  96. * = 3341ps
  97. * = 3.341ns
  98. *
  99. * Maximum delay calc (Ch 0):
  100. * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
  101. * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps
  102. * = 5673ps
  103. * = 5.673ns
  104. *
  105. * Minimum delay calc (Ch 1):
  106. * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
  107. * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
  108. * = 2822ps
  109. * = 2.822ns
  110. *
  111. * Maximum delay calc (Ch 1):
  112. * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
  113. * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps
  114. * = 4968ps
  115. * = 4.968ns
  116. *
  117. * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
  118. * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
  119. * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
  120. * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
  121. *
  122. * Write latency (WR_DATA_DELAY) is calculated by doing the following:
  123. *
  124. * The DDR SDRAM specification requires DQS be received no sooner than
  125. * 75% of an SDRAM clock period—and no later than 125% of a clock
  126. * period—from the capturing clock edge of the command/address at the
  127. * SDRAM.
  128. *
  129. * Based on the above tracelengths, the following are calculated:
  130. * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
  131. * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
  132. * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
  133. * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
  134. *
  135. * Difference in arrival time CLK vs. DQS:
  136. * Ch. 0 0.072ns
  137. * Ch. 1 0.138ns
  138. *
  139. * Both of these values are much less than 25% of the clock
  140. * period at DDR2-600 or DDR2-800, so no additional delay is needed over
  141. * the 1/2 cycle which normally aligns the first DQS transition
  142. * exactly WL (CAS latency minus one cycle) after the CAS strobe.
  143. * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
  144. * terminology corresponds to exactly one clock period delay after
  145. * the CAS strobe. (due to the fact that the "delay" is referenced
  146. * from the *falling* edge of the CLK, just after the rising edge
  147. * which the CAS strobe is latched on.
  148. */
  149. typedef struct board_memctl_options {
  150. uint16_t datarate_mhz_low;
  151. uint16_t datarate_mhz_high;
  152. uint8_t clk_adjust;
  153. uint8_t cpo_override;
  154. uint8_t write_data_delay;
  155. } board_memctl_options_t;
  156. static struct board_memctl_options bopts_ctrl[][2] = {
  157. {
  158. /* Controller 0 */
  159. {
  160. /* DDR2 600/667 */
  161. .datarate_mhz_low = 500,
  162. .datarate_mhz_high = 750,
  163. .clk_adjust = 5,
  164. .cpo_override = 8,
  165. .write_data_delay = 2,
  166. },
  167. {
  168. /* DDR2 800 */
  169. .datarate_mhz_low = 750,
  170. .datarate_mhz_high = 850,
  171. .clk_adjust = 5,
  172. .cpo_override = 9,
  173. .write_data_delay = 2,
  174. },
  175. },
  176. {
  177. /* Controller 1 */
  178. {
  179. /* DDR2 600/667 */
  180. .datarate_mhz_low = 500,
  181. .datarate_mhz_high = 750,
  182. .clk_adjust = 5,
  183. .cpo_override = 7,
  184. .write_data_delay = 2,
  185. },
  186. {
  187. /* DDR2 800 */
  188. .datarate_mhz_low = 750,
  189. .datarate_mhz_high = 850,
  190. .clk_adjust = 5,
  191. .cpo_override = 8,
  192. .write_data_delay = 2,
  193. },
  194. },
  195. };
  196. void fsl_ddr_board_options(memctl_options_t *popts,
  197. dimm_params_t *pdimm,
  198. unsigned int ctrl_num)
  199. {
  200. struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
  201. sys_info_t sysinfo;
  202. int i;
  203. unsigned int datarate;
  204. get_sys_info(&sysinfo);
  205. datarate = sysinfo.freq_ddrbus / 1000 / 1000;
  206. for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
  207. if ((bopts[i].datarate_mhz_low <= datarate) &&
  208. (bopts[i].datarate_mhz_high >= datarate)) {
  209. debug("controller %d:\n", ctrl_num);
  210. debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
  211. debug(" cpo = %d\n", bopts[i].cpo_override);
  212. debug(" write_data_delay = %d\n",
  213. bopts[i].write_data_delay);
  214. popts->clk_adjust = bopts[i].clk_adjust;
  215. popts->cpo_override = bopts[i].cpo_override;
  216. popts->write_data_delay = bopts[i].write_data_delay;
  217. }
  218. }
  219. /*
  220. * Factors to consider for half-strength driver enable:
  221. * - number of DIMMs installed
  222. */
  223. popts->half_strength_driver_enable = 0;
  224. }