fsl_8xxx_clk.c 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008 Extreme Engineering Solutions, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. /*
  8. * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
  9. */
  10. unsigned long get_board_sys_clk(ulong dummy)
  11. {
  12. #if defined(CONFIG_MPC85xx)
  13. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  14. #elif defined(CONFIG_MPC86xx)
  15. immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  16. volatile ccsr_gur_t *gur = &immap->im_gur;
  17. #endif
  18. if (in_be32(&gur->gpporcr) & 0x10000)
  19. return 66666666;
  20. else
  21. #ifdef CONFIG_ARCH_P2020
  22. return 100000000;
  23. #else
  24. return 50000000;
  25. #endif
  26. }
  27. #ifdef CONFIG_MPC85xx
  28. /*
  29. * Return DDR input clock - synchronous with SYSCLK or 66 MHz
  30. * Note: 86xx doesn't support asynchronous DDR clk
  31. */
  32. unsigned long get_board_ddr_clk(ulong dummy)
  33. {
  34. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  35. u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
  36. if (ddr_ratio == 0x7)
  37. return get_board_sys_clk(dummy);
  38. #ifdef CONFIG_ARCH_P2020
  39. if (in_be32(&gur->gpporcr) & 0x20000)
  40. return 66666666;
  41. else
  42. return 100000000;
  43. #else
  44. return 66666666;
  45. #endif
  46. }
  47. #endif