spl.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Wandboard
  4. * Author: Tungyi Lin <tungyilin1127@gmail.com>
  5. * Richard Hu <hakahu@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <linux/delay.h>
  14. #include <linux/errno.h>
  15. #include <asm/gpio.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/video.h>
  18. #include <mmc.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <asm/arch/crm_regs.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <spl.h>
  24. #include <asm/arch/mx6-ddr.h>
  25. /*
  26. * Driving strength:
  27. * 0x30 == 40 Ohm
  28. * 0x28 == 48 Ohm
  29. */
  30. #define IMX6DQ_DRIVE_STRENGTH 0x30
  31. #define IMX6SDL_DRIVE_STRENGTH 0x28
  32. #define IMX6QP_DRIVE_STRENGTH 0x28
  33. /* configure MX6Q/DUAL mmdc DDR io registers */
  34. static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  35. .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  36. .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  37. .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  38. .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  39. .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  40. .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  41. .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  42. .dram_sdba2 = 0x00000000,
  43. .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  44. .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  45. .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  46. .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  47. .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  48. .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  49. .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  50. .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  51. .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  52. .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  53. .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  54. .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  55. .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  56. .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  57. .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  58. .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  59. .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  60. .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  61. };
  62. /* configure MX6QP mmdc DDR io registers */
  63. static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
  64. .dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
  65. .dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
  66. .dram_cas = IMX6QP_DRIVE_STRENGTH,
  67. .dram_ras = IMX6QP_DRIVE_STRENGTH,
  68. .dram_reset = IMX6QP_DRIVE_STRENGTH,
  69. .dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
  70. .dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
  71. .dram_sdba2 = 0x00000000,
  72. .dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
  73. .dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
  74. .dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
  75. .dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
  76. .dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
  77. .dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
  78. .dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
  79. .dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
  80. .dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
  81. .dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
  82. .dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
  83. .dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
  84. .dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
  85. .dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
  86. .dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
  87. .dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
  88. .dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
  89. .dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
  90. };
  91. /* configure MX6Q/DUAL mmdc GRP io registers */
  92. static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  93. .grp_ddr_type = 0x000c0000,
  94. .grp_ddrmode_ctl = 0x00020000,
  95. .grp_ddrpke = 0x00000000,
  96. .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  97. .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  98. .grp_ddrmode = 0x00020000,
  99. .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  100. .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  101. .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  102. .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  103. .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  104. .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  105. .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  106. .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  107. };
  108. /* configure MX6QP mmdc GRP io registers */
  109. static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
  110. .grp_ddr_type = 0x000c0000,
  111. .grp_ddrmode_ctl = 0x00020000,
  112. .grp_ddrpke = 0x00000000,
  113. .grp_addds = IMX6QP_DRIVE_STRENGTH,
  114. .grp_ctlds = IMX6QP_DRIVE_STRENGTH,
  115. .grp_ddrmode = 0x00020000,
  116. .grp_b0ds = IMX6QP_DRIVE_STRENGTH,
  117. .grp_b1ds = IMX6QP_DRIVE_STRENGTH,
  118. .grp_b2ds = IMX6QP_DRIVE_STRENGTH,
  119. .grp_b3ds = IMX6QP_DRIVE_STRENGTH,
  120. .grp_b4ds = IMX6QP_DRIVE_STRENGTH,
  121. .grp_b5ds = IMX6QP_DRIVE_STRENGTH,
  122. .grp_b6ds = IMX6QP_DRIVE_STRENGTH,
  123. .grp_b7ds = IMX6QP_DRIVE_STRENGTH,
  124. };
  125. /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  126. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  127. .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  128. .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  129. .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  130. .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  131. .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  132. .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  133. .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  134. .dram_sdba2 = 0x00000000,
  135. .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  136. .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  137. .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  138. .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  139. .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  140. .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  141. .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  142. .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  143. .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  144. .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  145. .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  146. .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  147. .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  148. .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  149. .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  150. .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  151. .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  152. .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  153. };
  154. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  155. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  156. .grp_ddr_type = 0x000c0000,
  157. .grp_ddrmode_ctl = 0x00020000,
  158. .grp_ddrpke = 0x00000000,
  159. .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  160. .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  161. .grp_ddrmode = 0x00020000,
  162. .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  163. .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  164. .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  165. .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  166. .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  167. .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  168. .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  169. .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  170. };
  171. /* H5T04G63AFR-PB */
  172. static struct mx6_ddr3_cfg h5t04g63afr = {
  173. .mem_speed = 1600,
  174. .density = 4,
  175. .width = 16,
  176. .banks = 8,
  177. .rowaddr = 15,
  178. .coladdr = 10,
  179. .pagesz = 2,
  180. .trcd = 1375,
  181. .trcmin = 4875,
  182. .trasmin = 3500,
  183. };
  184. /* H5TQ2G63DFR-H9 */
  185. static struct mx6_ddr3_cfg h5tq2g63dfr = {
  186. .mem_speed = 1333,
  187. .density = 2,
  188. .width = 16,
  189. .banks = 8,
  190. .rowaddr = 14,
  191. .coladdr = 10,
  192. .pagesz = 2,
  193. .trcd = 1350,
  194. .trcmin = 4950,
  195. .trasmin = 3600,
  196. };
  197. static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
  198. .p0_mpwldectrl0 = 0x001f001f,
  199. .p0_mpwldectrl1 = 0x001f001f,
  200. .p1_mpwldectrl0 = 0x001f001f,
  201. .p1_mpwldectrl1 = 0x001f001f,
  202. .p0_mpdgctrl0 = 0x4301030d,
  203. .p0_mpdgctrl1 = 0x03020277,
  204. .p1_mpdgctrl0 = 0x4300030a,
  205. .p1_mpdgctrl1 = 0x02780248,
  206. .p0_mprddlctl = 0x4536393b,
  207. .p1_mprddlctl = 0x36353441,
  208. .p0_mpwrdlctl = 0x41414743,
  209. .p1_mpwrdlctl = 0x462f453f,
  210. };
  211. /* DDR 64bit 2GB */
  212. static struct mx6_ddr_sysinfo mem_q = {
  213. .dsize = 2,
  214. .cs1_mirror = 0,
  215. /* config for full 4GB range so that get_mem_size() works */
  216. .cs_density = 32,
  217. .ncs = 1,
  218. .bi_on = 1,
  219. .rtt_nom = 1,
  220. .rtt_wr = 0,
  221. .ralat = 5,
  222. .walat = 0,
  223. .mif3_mode = 3,
  224. .rst_to_cke = 0x23,
  225. .sde_to_rst = 0x10,
  226. .refsel = 1, /* Refresh cycles at 32KHz */
  227. .refr = 3, /* 4 refresh commands per refresh cycle */
  228. };
  229. static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
  230. .p0_mpwldectrl0 = 0x001f001f,
  231. .p0_mpwldectrl1 = 0x001f001f,
  232. .p1_mpwldectrl0 = 0x001f001f,
  233. .p1_mpwldectrl1 = 0x001f001f,
  234. .p0_mpdgctrl0 = 0x420e020e,
  235. .p0_mpdgctrl1 = 0x02000200,
  236. .p1_mpdgctrl0 = 0x42020202,
  237. .p1_mpdgctrl1 = 0x01720172,
  238. .p0_mprddlctl = 0x494c4f4c,
  239. .p1_mprddlctl = 0x4a4c4c49,
  240. .p0_mpwrdlctl = 0x3f3f3133,
  241. .p1_mpwrdlctl = 0x39373f2e,
  242. };
  243. static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
  244. .p0_mpwldectrl0 = 0x0040003c,
  245. .p0_mpwldectrl1 = 0x0032003e,
  246. .p0_mpdgctrl0 = 0x42350231,
  247. .p0_mpdgctrl1 = 0x021a0218,
  248. .p0_mprddlctl = 0x4b4b4e49,
  249. .p0_mpwrdlctl = 0x3f3f3035,
  250. };
  251. /* DDR 64bit 1GB */
  252. static struct mx6_ddr_sysinfo mem_dl = {
  253. .dsize = 2,
  254. .cs1_mirror = 0,
  255. /* config for full 4GB range so that get_mem_size() works */
  256. .cs_density = 32,
  257. .ncs = 1,
  258. .bi_on = 1,
  259. .rtt_nom = 1,
  260. .rtt_wr = 0,
  261. .ralat = 5,
  262. .walat = 0,
  263. .mif3_mode = 3,
  264. .rst_to_cke = 0x23,
  265. .sde_to_rst = 0x10,
  266. .refsel = 1, /* Refresh cycles at 32KHz */
  267. .refr = 3, /* 4 refresh commands per refresh cycle */
  268. };
  269. /* DDR 32bit 512MB */
  270. static struct mx6_ddr_sysinfo mem_s = {
  271. .dsize = 1,
  272. .cs1_mirror = 0,
  273. /* config for full 4GB range so that get_mem_size() works */
  274. .cs_density = 32,
  275. .ncs = 1,
  276. .bi_on = 1,
  277. .rtt_nom = 1,
  278. .rtt_wr = 0,
  279. .ralat = 5,
  280. .walat = 0,
  281. .mif3_mode = 3,
  282. .rst_to_cke = 0x23,
  283. .sde_to_rst = 0x10,
  284. .refsel = 1, /* Refresh cycles at 32KHz */
  285. .refr = 3, /* 4 refresh commands per refresh cycle */
  286. };
  287. static void ccgr_init(void)
  288. {
  289. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  290. writel(0x00C03F3F, &ccm->CCGR0);
  291. writel(0x0030FC03, &ccm->CCGR1);
  292. writel(0x0FFFC000, &ccm->CCGR2);
  293. writel(0x3FF03000, &ccm->CCGR3);
  294. writel(0x00FFF300, &ccm->CCGR4);
  295. writel(0x0F0000C3, &ccm->CCGR5);
  296. writel(0x000003FF, &ccm->CCGR6);
  297. }
  298. static void spl_dram_init_imx6qp_lpddr3(void)
  299. {
  300. /* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
  301. writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
  302. /* Calibrations - ZQ */
  303. writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
  304. /* write leveling */
  305. writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
  306. writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
  307. writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
  308. writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
  309. /*
  310. * DQS gating, read delay, write delay calibration values
  311. * based on calibration compare of 0x00ffff00
  312. */
  313. writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
  314. writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
  315. writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
  316. writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
  317. writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
  318. writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
  319. writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
  320. writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
  321. writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
  322. writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
  323. writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
  324. writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
  325. writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
  326. writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
  327. writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
  328. writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
  329. writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
  330. writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
  331. writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
  332. writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
  333. /* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
  334. writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
  335. writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
  336. writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
  337. writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
  338. writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
  339. writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
  340. writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
  341. writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
  342. writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
  343. writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
  344. writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
  345. writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
  346. writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
  347. /* add NOC DDR configuration */
  348. writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
  349. writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
  350. writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
  351. writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
  352. writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
  353. writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
  354. writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
  355. writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
  356. writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
  357. writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
  358. writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
  359. writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
  360. writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
  361. writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
  362. writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
  363. writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
  364. writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
  365. }
  366. static void spl_dram_init(void)
  367. {
  368. if (is_mx6dqp()) {
  369. mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
  370. spl_dram_init_imx6qp_lpddr3();
  371. } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
  372. mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  373. mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
  374. } else if (is_cpu_type(MXC_CPU_MX6DL)) {
  375. mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  376. mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
  377. } else if (is_cpu_type(MXC_CPU_MX6Q)) {
  378. mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
  379. mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
  380. }
  381. udelay(100);
  382. }
  383. void board_init_f(ulong dummy)
  384. {
  385. ccgr_init();
  386. /* setup AIPS and disable watchdog */
  387. arch_cpu_init();
  388. gpr_init();
  389. /* iomux */
  390. board_early_init_f();
  391. /* setup GP timer */
  392. timer_init();
  393. /* UART clocks enabled and gd valid - init serial console */
  394. preloader_console_init();
  395. /* DDR initialization */
  396. spl_dram_init();
  397. }
  398. #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
  399. #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
  400. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  401. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  402. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  403. static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  404. {USDHC3_BASE_ADDR},
  405. {USDHC1_BASE_ADDR},
  406. };
  407. static iomux_v3_cfg_t const usdhc1_pads[] = {
  408. IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  409. IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  410. IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  411. IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  412. IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  413. IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  414. /* Carrier MicroSD Card Detect */
  415. IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  416. };
  417. static iomux_v3_cfg_t const usdhc3_pads[] = {
  418. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  419. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  420. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  421. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  422. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  423. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  424. /* SOM MicroSD Card Detect */
  425. IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  426. };
  427. int board_mmc_getcd(struct mmc *mmc)
  428. {
  429. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  430. int ret = 0;
  431. switch (cfg->esdhc_base) {
  432. case USDHC1_BASE_ADDR:
  433. ret = !gpio_get_value(USDHC1_CD_GPIO);
  434. break;
  435. case USDHC3_BASE_ADDR:
  436. ret = !gpio_get_value(USDHC3_CD_GPIO);
  437. break;
  438. }
  439. return ret;
  440. }
  441. int board_mmc_init(struct bd_info *bis)
  442. {
  443. int ret;
  444. u32 index = 0;
  445. /*
  446. * Following map is done:
  447. * (U-Boot device node) (Physical Port)
  448. * mmc0 SOM MicroSD
  449. * mmc1 Carrier board MicroSD
  450. */
  451. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  452. switch (index) {
  453. case 0:
  454. SETUP_IOMUX_PADS(usdhc3_pads);
  455. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  456. usdhc_cfg[0].max_bus_width = 4;
  457. gpio_direction_input(USDHC3_CD_GPIO);
  458. break;
  459. case 1:
  460. SETUP_IOMUX_PADS(usdhc1_pads);
  461. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  462. usdhc_cfg[1].max_bus_width = 4;
  463. gpio_direction_input(USDHC1_CD_GPIO);
  464. break;
  465. default:
  466. printf("Warning: you configured more USDHC controllers"
  467. "(%d) then supported by the board (%d)\n",
  468. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  469. return -EINVAL;
  470. }
  471. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  472. if (ret)
  473. return ret;
  474. }
  475. return 0;
  476. }