pico-imx7d.c 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 NXP Semiconductors
  4. */
  5. #include <init.h>
  6. #include <net.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/crm_regs.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/mx7-pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/gpio.h>
  13. #include <asm/mach-imx/iomux-v3.h>
  14. #include <asm/mach-imx/mxc_i2c.h>
  15. #include <asm/io.h>
  16. #include <common.h>
  17. #include <i2c.h>
  18. #include <miiphy.h>
  19. #include <power/pmic.h>
  20. #include <power/pfuze3000_pmic.h>
  21. #include "../../freescale/common/pfuze.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
  24. PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  25. #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  26. PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  27. #ifdef CONFIG_SYS_I2C_MXC
  28. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  29. /* I2C4 for PMIC */
  30. static struct i2c_pads_info i2c_pad_info4 = {
  31. .scl = {
  32. .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
  33. .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
  34. .gp = IMX_GPIO_NR(6, 16),
  35. },
  36. .sda = {
  37. .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
  38. .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
  39. .gp = IMX_GPIO_NR(6, 17),
  40. },
  41. };
  42. #endif
  43. int dram_init(void)
  44. {
  45. gd->ram_size = imx_ddr_size();
  46. /* Subtract the defined OPTEE runtime firmware length */
  47. #ifdef CONFIG_OPTEE_TZDRAM_SIZE
  48. gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
  49. #endif
  50. return 0;
  51. }
  52. #ifdef CONFIG_POWER
  53. #define I2C_PMIC 3
  54. int power_init_board(void)
  55. {
  56. struct pmic *p;
  57. int ret;
  58. unsigned int reg, rev_id;
  59. ret = power_pfuze3000_init(I2C_PMIC);
  60. if (ret)
  61. return ret;
  62. p = pmic_get("PFUZE3000");
  63. ret = pmic_probe(p);
  64. if (ret) {
  65. printf("Warning: Cannot find PMIC PFUZE3000\n");
  66. printf("\tPower consumption is not optimized.\n");
  67. return 0;
  68. }
  69. pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
  70. pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
  71. printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  72. /* disable Low Power Mode during standby mode */
  73. pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
  74. reg |= 0x1;
  75. pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
  76. /* SW1A/1B mode set to APS/APS */
  77. reg = 0x8;
  78. pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
  79. pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
  80. /* SW1A/1B standby voltage set to 1.025V */
  81. reg = 0xd;
  82. pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
  83. pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
  84. /* decrease SW1B normal voltage to 0.975V */
  85. pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
  86. reg &= ~0x1f;
  87. reg |= PFUZE3000_SW1AB_SETP(975);
  88. pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
  89. return 0;
  90. }
  91. #endif
  92. static iomux_v3_cfg_t const wdog_pads[] = {
  93. MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  94. };
  95. static iomux_v3_cfg_t const uart5_pads[] = {
  96. MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  97. MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  98. };
  99. #ifdef CONFIG_FEC_MXC
  100. static int setup_fec(void)
  101. {
  102. struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  103. = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  104. /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
  105. clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  106. (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
  107. IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
  108. return set_clk_enet(ENET_125MHZ);
  109. }
  110. int board_phy_config(struct phy_device *phydev)
  111. {
  112. unsigned short val;
  113. /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
  114. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  115. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  116. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  117. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  118. val &= 0xffe7;
  119. val |= 0x18;
  120. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  121. /* introduce tx clock delay */
  122. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  123. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  124. val |= 0x0100;
  125. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  126. if (phydev->drv->config)
  127. phydev->drv->config(phydev);
  128. return 0;
  129. }
  130. #endif
  131. static void setup_iomux_uart(void)
  132. {
  133. imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
  134. }
  135. int board_early_init_f(void)
  136. {
  137. setup_iomux_uart();
  138. #ifdef CONFIG_SYS_I2C_MXC
  139. setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
  140. #endif
  141. return 0;
  142. }
  143. #ifdef CONFIG_DM_VIDEO
  144. void setup_lcd(void)
  145. {
  146. gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness");
  147. gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable");
  148. /* Set Brightness to high */
  149. gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
  150. /* Set LCD enable to high */
  151. gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
  152. }
  153. #endif
  154. int board_init(void)
  155. {
  156. /* address of boot parameters */
  157. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  158. #ifdef CONFIG_DM_VIDEO
  159. setup_lcd();
  160. #endif
  161. #ifdef CONFIG_FEC_MXC
  162. setup_fec();
  163. #endif
  164. return 0;
  165. }
  166. int board_late_init(void)
  167. {
  168. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  169. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  170. set_wdog_reset(wdog);
  171. /*
  172. * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
  173. * since we use PMIC_PWRON to reset the board.
  174. */
  175. clrsetbits_le16(&wdog->wcr, 0, 0x10);
  176. return 0;
  177. }
  178. int checkboard(void)
  179. {
  180. puts("Board: i.MX7D PICOSOM\n");
  181. return 0;
  182. }
  183. static iomux_v3_cfg_t const usb_otg2_pads[] = {
  184. MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  185. };
  186. int board_ehci_hcd_init(int port)
  187. {
  188. switch (port) {
  189. case 0:
  190. break;
  191. case 1:
  192. imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
  193. ARRAY_SIZE(usb_otg2_pads));
  194. break;
  195. default:
  196. return -EINVAL;
  197. }
  198. return 0;
  199. }