tbs2910.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Soeren Moch <smoch@web.de>
  4. */
  5. #include <init.h>
  6. #include <asm/arch/clock.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/iomux.h>
  9. #include <asm/arch/mx6-pins.h>
  10. #include <linux/errno.h>
  11. #include <asm/gpio.h>
  12. #include <asm/mach-imx/iomux-v3.h>
  13. #include <asm/mach-imx/boot_mode.h>
  14. #include <asm/mach-imx/video.h>
  15. #include <mmc.h>
  16. #include <fsl_esdhc_imx.h>
  17. #include <asm/arch/mxc_hdmi.h>
  18. #include <asm/arch/crm_regs.h>
  19. #include <asm/io.h>
  20. #include <asm/arch/sys_proto.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  23. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  24. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  25. static iomux_v3_cfg_t const uart1_pads[] = {
  26. MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  27. MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  28. };
  29. static iomux_v3_cfg_t const uart2_pads[] = {
  30. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  31. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  32. };
  33. int dram_init(void)
  34. {
  35. gd->ram_size = 2048ul * 1024 * 1024;
  36. return 0;
  37. }
  38. static void setup_iomux_uart(void)
  39. {
  40. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  41. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  42. }
  43. #ifdef CONFIG_FSL_ESDHC_IMX
  44. /* set environment device to boot device when booting from SD */
  45. int board_mmc_get_env_dev(int devno)
  46. {
  47. return devno - 1;
  48. }
  49. int board_mmc_get_env_part(int devno)
  50. {
  51. return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
  52. }
  53. #endif /* CONFIG_FSL_ESDHC_IMX */
  54. #ifdef CONFIG_VIDEO_IPUV3
  55. static void do_enable_hdmi(struct display_info_t const *dev)
  56. {
  57. imx_enable_hdmi_phy();
  58. }
  59. struct display_info_t const displays[] = {{
  60. .bus = -1,
  61. .addr = 0,
  62. .pixfmt = IPU_PIX_FMT_RGB24,
  63. .detect = detect_hdmi,
  64. .enable = do_enable_hdmi,
  65. .mode = {
  66. .name = "HDMI",
  67. /* 1024x768@60Hz (VESA)*/
  68. .refresh = 60,
  69. .xres = 1024,
  70. .yres = 768,
  71. .pixclock = 15384,
  72. .left_margin = 160,
  73. .right_margin = 24,
  74. .upper_margin = 29,
  75. .lower_margin = 3,
  76. .hsync_len = 136,
  77. .vsync_len = 6,
  78. .sync = FB_SYNC_EXT,
  79. .vmode = FB_VMODE_NONINTERLACED
  80. } } };
  81. size_t display_count = ARRAY_SIZE(displays);
  82. static void setup_display(void)
  83. {
  84. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  85. int reg;
  86. s32 timeout = 100000;
  87. enable_ipu_clock();
  88. imx_setup_hdmi();
  89. /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
  90. reg = readl(&ccm->analog_pll_video);
  91. reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
  92. writel(reg, &ccm->analog_pll_video);
  93. reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  94. reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
  95. reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  96. reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
  97. writel(reg, &ccm->analog_pll_video);
  98. writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
  99. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
  100. reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
  101. writel(reg, &ccm->analog_pll_video);
  102. while (timeout--)
  103. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  104. break;
  105. if (timeout < 0)
  106. printf("Warning: video pll lock timeout!\n");
  107. reg = readl(&ccm->analog_pll_video);
  108. reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
  109. reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
  110. writel(reg, &ccm->analog_pll_video);
  111. /* gate ipu1_di0_clk */
  112. reg = readl(&ccm->CCGR3);
  113. reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
  114. writel(reg, &ccm->CCGR3);
  115. /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
  116. reg = readl(&ccm->chsccdr);
  117. reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
  118. MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
  119. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  120. reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
  121. (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
  122. (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  123. writel(reg, &ccm->chsccdr);
  124. /* enable ipu1_di0_clk */
  125. reg = readl(&ccm->CCGR3);
  126. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  127. writel(reg, &ccm->CCGR3);
  128. }
  129. #endif /* CONFIG_VIDEO_IPUV3 */
  130. int board_early_init_f(void)
  131. {
  132. setup_iomux_uart();
  133. return 0;
  134. }
  135. #ifdef CONFIG_CMD_BMODE
  136. static const struct boot_mode board_boot_modes[] = {
  137. /* 4 bit bus width */
  138. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  139. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  140. /* 8 bit bus width */
  141. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  142. {NULL, 0},
  143. };
  144. #endif
  145. int board_init(void)
  146. {
  147. /* address of boot parameters */
  148. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  149. #ifdef CONFIG_VIDEO_IPUV3
  150. setup_display();
  151. #endif
  152. #ifdef CONFIG_CMD_BMODE
  153. add_board_boot_modes(board_boot_modes);
  154. #endif
  155. return 0;
  156. }