nand.c 3.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008
  4. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  5. */
  6. #include <common.h>
  7. #if defined(CONFIG_SYS_NAND_BASE)
  8. #include <nand.h>
  9. #include <linux/errno.h>
  10. #include <asm/io.h>
  11. static int state;
  12. static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte);
  13. static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
  14. static u_char sc_nand_read_byte(struct mtd_info *mtd);
  15. static u16 sc_nand_read_word(struct mtd_info *mtd);
  16. static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
  17. static int sc_nand_device_ready(struct mtd_info *mtdinfo);
  18. #define FPGA_NAND_CMD_MASK (0x7 << 28)
  19. #define FPGA_NAND_CMD_COMMAND (0x0 << 28)
  20. #define FPGA_NAND_CMD_ADDR (0x1 << 28)
  21. #define FPGA_NAND_CMD_READ (0x2 << 28)
  22. #define FPGA_NAND_CMD_WRITE (0x3 << 28)
  23. #define FPGA_NAND_BUSY (0x1 << 15)
  24. #define FPGA_NAND_ENABLE (0x1 << 31)
  25. #define FPGA_NAND_DATA_SHIFT 16
  26. /**
  27. * sc_nand_write_byte - write one byte to the chip
  28. * @mtd: MTD device structure
  29. * @byte: pointer to data byte to write
  30. */
  31. static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte)
  32. {
  33. sc_nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
  34. }
  35. /**
  36. * sc_nand_write_buf - write buffer to chip
  37. * @mtd: MTD device structure
  38. * @buf: data buffer
  39. * @len: number of bytes to write
  40. */
  41. static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  42. {
  43. int i;
  44. struct nand_chip *this = mtd_to_nand(mtd);
  45. for (i = 0; i < len; i++) {
  46. out_be32(this->IO_ADDR_W,
  47. state | (buf[i] << FPGA_NAND_DATA_SHIFT));
  48. }
  49. }
  50. /**
  51. * sc_nand_read_byte - read one byte from the chip
  52. * @mtd: MTD device structure
  53. */
  54. static u_char sc_nand_read_byte(struct mtd_info *mtd)
  55. {
  56. u8 byte;
  57. sc_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
  58. return byte;
  59. }
  60. /**
  61. * sc_nand_read_word - read one word from the chip
  62. * @mtd: MTD device structure
  63. */
  64. static u16 sc_nand_read_word(struct mtd_info *mtd)
  65. {
  66. u16 word;
  67. sc_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
  68. return word;
  69. }
  70. /**
  71. * sc_nand_read_buf - read chip data into buffer
  72. * @mtd: MTD device structure
  73. * @buf: buffer to store date
  74. * @len: number of bytes to read
  75. */
  76. static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  77. {
  78. int i;
  79. struct nand_chip *this = mtd_to_nand(mtd);
  80. int val;
  81. val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;
  82. out_be32(this->IO_ADDR_W, val);
  83. for (i = 0; i < len; i++) {
  84. buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff;
  85. }
  86. }
  87. /**
  88. * sc_nand_device_ready - Check the NAND device is ready for next command.
  89. * @mtd: MTD device structure
  90. */
  91. static int sc_nand_device_ready(struct mtd_info *mtdinfo)
  92. {
  93. struct nand_chip *this = mtd_to_nand(mtdinfo);
  94. if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
  95. return 0; /* busy */
  96. return 1;
  97. }
  98. /**
  99. * sc_nand_hwcontrol - NAND control functions wrapper.
  100. * @mtd: MTD device structure
  101. * @cmd: Command
  102. */
  103. static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
  104. {
  105. if (ctrl & NAND_CTRL_CHANGE) {
  106. state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE);
  107. switch (ctrl & (NAND_ALE | NAND_CLE)) {
  108. case 0:
  109. state |= FPGA_NAND_CMD_WRITE;
  110. break;
  111. case NAND_ALE:
  112. state |= FPGA_NAND_CMD_ADDR;
  113. break;
  114. case NAND_CLE:
  115. state |= FPGA_NAND_CMD_COMMAND;
  116. break;
  117. default:
  118. printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
  119. }
  120. if (ctrl & NAND_NCE)
  121. state |= FPGA_NAND_ENABLE;
  122. }
  123. if (cmd != NAND_CMD_NONE)
  124. sc_nand_write_byte(mtdinfo, cmd);
  125. }
  126. int board_nand_init(struct nand_chip *nand)
  127. {
  128. nand->cmd_ctrl = sc_nand_hwcontrol;
  129. nand->ecc.mode = NAND_ECC_SOFT;
  130. nand->dev_ready = sc_nand_device_ready;
  131. nand->read_byte = sc_nand_read_byte;
  132. nand->read_word = sc_nand_read_word;
  133. nand->write_buf = sc_nand_write_buf;
  134. nand->read_buf = sc_nand_read_buf;
  135. return 0;
  136. }
  137. #endif