board.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for TI AM335X based pxm2 board
  4. * (C) Copyright 2013 Siemens Schweiz AG
  5. * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. *
  7. * Based on:
  8. * u-boot:/board/ti/am335x/board.c
  9. *
  10. * Board functions for TI AM335X based boards
  11. *
  12. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  13. */
  14. #include <common.h>
  15. #include <env.h>
  16. #include <errno.h>
  17. #include <init.h>
  18. #include <log.h>
  19. #include <malloc.h>
  20. #include <net.h>
  21. #include <spl.h>
  22. #include <asm/arch/cpu.h>
  23. #include <asm/arch/hardware.h>
  24. #include <asm/arch/omap.h>
  25. #include <asm/arch/ddr_defs.h>
  26. #include <asm/arch/clock.h>
  27. #include <asm/arch/gpio.h>
  28. #include <asm/arch/mmc_host_def.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include "../../../drivers/video/da8xx-fb.h"
  31. #include <asm/io.h>
  32. #include <asm/emif.h>
  33. #include <asm/gpio.h>
  34. #include <i2c.h>
  35. #include <miiphy.h>
  36. #include <cpsw.h>
  37. #include <watchdog.h>
  38. #include "board.h"
  39. #include "../common/factoryset.h"
  40. #include "pmic.h"
  41. #include <nand.h>
  42. #include <bmp_layout.h>
  43. #ifdef CONFIG_SPL_BUILD
  44. static void board_init_ddr(void)
  45. {
  46. struct emif_regs pxm2_ddr3_emif_reg_data = {
  47. .sdram_config = 0x41805332,
  48. .sdram_tim1 = 0x666b3c9,
  49. .sdram_tim2 = 0x243631ca,
  50. .sdram_tim3 = 0x33f,
  51. .emif_ddr_phy_ctlr_1 = 0x100005,
  52. .zq_config = 0,
  53. .ref_ctrl = 0x81a,
  54. };
  55. struct ddr_data pxm2_ddr3_data = {
  56. .datardsratio0 = 0x81204812,
  57. .datawdsratio0 = 0,
  58. .datafwsratio0 = 0x8020080,
  59. .datawrsratio0 = 0x4010040,
  60. };
  61. struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
  62. .cmd0csratio = 0x80,
  63. .cmd0iclkout = 0,
  64. .cmd1csratio = 0x80,
  65. .cmd1iclkout = 0,
  66. .cmd2csratio = 0x80,
  67. .cmd2iclkout = 0,
  68. };
  69. const struct ctrl_ioregs ioregs = {
  70. .cm0ioctl = DDR_IOCTRL_VAL,
  71. .cm1ioctl = DDR_IOCTRL_VAL,
  72. .cm2ioctl = DDR_IOCTRL_VAL,
  73. .dt0ioctl = DDR_IOCTRL_VAL,
  74. .dt1ioctl = DDR_IOCTRL_VAL,
  75. };
  76. config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
  77. &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
  78. }
  79. /*
  80. * voltage switching for MPU frequency switching.
  81. * @module = mpu - 0, core - 1
  82. * @vddx_op_vol_sel = vdd voltage to set
  83. */
  84. #define MPU 0
  85. #define CORE 1
  86. int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
  87. {
  88. uchar buf[4];
  89. unsigned int reg_offset;
  90. if (module == MPU)
  91. reg_offset = PMIC_VDD1_OP_REG;
  92. else
  93. reg_offset = PMIC_VDD2_OP_REG;
  94. /* Select VDDx OP */
  95. if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
  96. return 1;
  97. buf[0] &= ~PMIC_OP_REG_CMD_MASK;
  98. if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
  99. return 1;
  100. /* Configure VDDx OP Voltage */
  101. if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
  102. return 1;
  103. buf[0] &= ~PMIC_OP_REG_SEL_MASK;
  104. buf[0] |= vddx_op_vol_sel;
  105. if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
  106. return 1;
  107. if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
  108. return 1;
  109. if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
  110. return 1;
  111. return 0;
  112. }
  113. #define OSC (V_OSCK/1000000)
  114. const struct dpll_params dpll_mpu_pxm2 = {
  115. 720, OSC-1, 1, -1, -1, -1, -1};
  116. void spl_siemens_board_init(void)
  117. {
  118. uchar buf[4];
  119. /*
  120. * pxm2 PMIC code. All boards currently want an MPU voltage
  121. * of 1.2625V and CORE voltage of 1.1375V to operate at
  122. * 720MHz.
  123. */
  124. if (i2c_probe(PMIC_CTRL_I2C_ADDR))
  125. return;
  126. /* VDD1/2 voltage selection register access by control i/f */
  127. if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
  128. return;
  129. buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
  130. if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
  131. return;
  132. /* Frequency switching for OPP 120 */
  133. if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
  134. voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
  135. printf("voltage update failed\n");
  136. }
  137. }
  138. #endif /* if def CONFIG_SPL_BUILD */
  139. int read_eeprom(void)
  140. {
  141. /* nothing ToDo here for this board */
  142. return 0;
  143. }
  144. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  145. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  146. static void cpsw_control(int enabled)
  147. {
  148. /* VTP can be added here */
  149. return;
  150. }
  151. static struct cpsw_slave_data cpsw_slaves[] = {
  152. {
  153. .slave_reg_ofs = 0x208,
  154. .sliver_reg_ofs = 0xd80,
  155. .phy_addr = 0,
  156. .phy_if = PHY_INTERFACE_MODE_RMII,
  157. },
  158. {
  159. .slave_reg_ofs = 0x308,
  160. .sliver_reg_ofs = 0xdc0,
  161. .phy_addr = 1,
  162. .phy_if = PHY_INTERFACE_MODE_RMII,
  163. },
  164. };
  165. static struct cpsw_platform_data cpsw_data = {
  166. .mdio_base = CPSW_MDIO_BASE,
  167. .cpsw_base = CPSW_BASE,
  168. .mdio_div = 0xff,
  169. .channels = 4,
  170. .cpdma_reg_ofs = 0x800,
  171. .slaves = 1,
  172. .slave_data = cpsw_slaves,
  173. .ale_reg_ofs = 0xd00,
  174. .ale_entries = 1024,
  175. .host_port_reg_ofs = 0x108,
  176. .hw_stats_reg_ofs = 0x900,
  177. .bd_ram_ofs = 0x2000,
  178. .mac_control = (1 << 5),
  179. .control = cpsw_control,
  180. .host_port_num = 0,
  181. .version = CPSW_CTRL_VERSION_2,
  182. };
  183. #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
  184. #if defined(CONFIG_DRIVER_TI_CPSW) || \
  185. (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
  186. int board_eth_init(struct bd_info *bis)
  187. {
  188. int n = 0;
  189. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  190. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  191. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  192. #ifdef CONFIG_FACTORYSET
  193. int rv;
  194. if (!is_valid_ethaddr(factory_dat.mac))
  195. printf("Error: no valid mac address\n");
  196. else
  197. eth_env_set_enetaddr("ethaddr", factory_dat.mac);
  198. #endif /* #ifdef CONFIG_FACTORYSET */
  199. /* Set rgmii mode and enable rmii clock to be sourced from chip */
  200. writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
  201. rv = cpsw_register(&cpsw_data);
  202. if (rv < 0)
  203. printf("Error %d registering CPSW switch\n", rv);
  204. else
  205. n += rv;
  206. #endif
  207. return n;
  208. }
  209. #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
  210. #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
  211. static struct da8xx_panel lcd_panels[] = {
  212. /* AUO G156XW01 V1 */
  213. [0] = {
  214. .name = "AUO_G156XW01_V1",
  215. .width = 1376,
  216. .height = 768,
  217. .hfp = 14,
  218. .hbp = 64,
  219. .hsw = 56,
  220. .vfp = 1,
  221. .vbp = 28,
  222. .vsw = 3,
  223. .pxl_clk = 60000000,
  224. .invert_pxl_clk = 0,
  225. },
  226. /* AUO B101EVN06 V0 */
  227. [1] = {
  228. .name = "AUO_B101EVN06_V0",
  229. .width = 1280,
  230. .height = 800,
  231. .hfp = 52,
  232. .hbp = 84,
  233. .hsw = 36,
  234. .vfp = 3,
  235. .vbp = 14,
  236. .vsw = 6,
  237. .pxl_clk = 60000000,
  238. .invert_pxl_clk = 0,
  239. },
  240. /*
  241. * Settings from factoryset
  242. * stored in EEPROM
  243. */
  244. [2] = {
  245. .name = "factoryset",
  246. .width = 0,
  247. .height = 0,
  248. .hfp = 0,
  249. .hbp = 0,
  250. .hsw = 0,
  251. .vfp = 0,
  252. .vbp = 0,
  253. .vsw = 0,
  254. .pxl_clk = 60000000,
  255. .invert_pxl_clk = 0,
  256. },
  257. };
  258. static const struct display_panel disp_panel = {
  259. WVGA,
  260. 32,
  261. 16,
  262. COLOR_ACTIVE,
  263. };
  264. static const struct lcd_ctrl_config lcd_cfg = {
  265. &disp_panel,
  266. .ac_bias = 255,
  267. .ac_bias_intrpt = 0,
  268. .dma_burst_sz = 16,
  269. .bpp = 32,
  270. .fdd = 0x80,
  271. .tft_alt_mode = 0,
  272. .stn_565_mode = 0,
  273. .mono_8bit_mode = 0,
  274. .invert_line_clock = 1,
  275. .invert_frm_clock = 1,
  276. .sync_edge = 0,
  277. .sync_ctrl = 1,
  278. .raster_order = 0,
  279. };
  280. static int set_gpio(int gpio, int state)
  281. {
  282. gpio_request(gpio, "temp");
  283. gpio_direction_output(gpio, state);
  284. gpio_set_value(gpio, state);
  285. gpio_free(gpio);
  286. return 0;
  287. }
  288. static int enable_backlight(void)
  289. {
  290. set_gpio(BOARD_LCD_POWER, 1);
  291. set_gpio(BOARD_BACK_LIGHT, 1);
  292. set_gpio(BOARD_TOUCH_POWER, 1);
  293. return 0;
  294. }
  295. static int enable_pwm(void)
  296. {
  297. struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
  298. struct pwmss_ecap_regs *ecap;
  299. int ticks = PWM_TICKS;
  300. int duty = PWM_DUTY;
  301. ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
  302. /* enable clock */
  303. setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
  304. /* TimeStam Counter register */
  305. writel(0xdb9, &ecap->tsctr);
  306. /* config period */
  307. writel(ticks - 1, &ecap->cap3);
  308. writel(ticks - 1, &ecap->cap1);
  309. setbits_le16(&ecap->ecctl2,
  310. (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
  311. /* config duty */
  312. writel(duty, &ecap->cap2);
  313. writel(duty, &ecap->cap4);
  314. /* start */
  315. setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
  316. return 0;
  317. }
  318. static struct dpll_regs dpll_lcd_regs = {
  319. .cm_clkmode_dpll = CM_WKUP + 0x98,
  320. .cm_idlest_dpll = CM_WKUP + 0x48,
  321. .cm_clksel_dpll = CM_WKUP + 0x54,
  322. };
  323. /* no console on this board */
  324. int board_cfb_skip(void)
  325. {
  326. return 1;
  327. }
  328. #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
  329. #define PLL_GET_N(v) (v & 0x7f)
  330. static int get_clk(struct dpll_regs *dpll_regs)
  331. {
  332. unsigned int val;
  333. unsigned int m, n;
  334. int f = 0;
  335. val = readl(dpll_regs->cm_clksel_dpll);
  336. m = PLL_GET_M(val);
  337. n = PLL_GET_N(val);
  338. f = (m * V_OSCK) / n;
  339. return f;
  340. };
  341. int clk_get(int clk)
  342. {
  343. return get_clk(&dpll_lcd_regs);
  344. };
  345. static int conf_disp_pll(int m, int n)
  346. {
  347. struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  348. struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
  349. struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
  350. u32 *const clk_domains[] = {
  351. &cmper->lcdclkctrl,
  352. 0
  353. };
  354. u32 *const clk_modules_explicit_en[] = {
  355. &cmper->lcdclkctrl,
  356. &cmper->lcdcclkstctrl,
  357. &cmper->epwmss0clkctrl,
  358. 0
  359. };
  360. do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
  361. writel(0x0, &cmdpll->clklcdcpixelclk);
  362. do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
  363. return 0;
  364. }
  365. static int board_video_init(void)
  366. {
  367. conf_disp_pll(24, 1);
  368. if (factory_dat.pxm50)
  369. da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
  370. else
  371. da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
  372. enable_pwm();
  373. enable_backlight();
  374. return 0;
  375. }
  376. #endif
  377. #ifdef CONFIG_BOARD_LATE_INIT
  378. int board_late_init(void)
  379. {
  380. int ret;
  381. omap_nand_switch_ecc(1, 8);
  382. #ifdef CONFIG_FACTORYSET
  383. if (factory_dat.asn[0] != 0) {
  384. char tmp[2 * MAX_STRING_LENGTH + 2];
  385. if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
  386. factory_dat.pxm50 = 1;
  387. else
  388. factory_dat.pxm50 = 0;
  389. sprintf(tmp, "%s_%s", factory_dat.asn,
  390. factory_dat.comp_version);
  391. ret = env_set("boardid", tmp);
  392. if (ret)
  393. printf("error setting board id\n");
  394. } else {
  395. factory_dat.pxm50 = 1;
  396. ret = env_set("boardid", "PXM50_1.0");
  397. if (ret)
  398. printf("error setting board id\n");
  399. }
  400. debug("PXM50: %d\n", factory_dat.pxm50);
  401. #endif
  402. return 0;
  403. }
  404. #endif
  405. #include "../common/board.c"