sbc8641d.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
  4. * Copyright 2007 Embedded Specialties, Inc.
  5. * Joe Hamman joe.hamman@embeddedspecialties.com
  6. *
  7. * Copyright 2004 Freescale Semiconductor.
  8. * Jeff Brown
  9. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  10. *
  11. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  12. */
  13. #include <common.h>
  14. #include <command.h>
  15. #include <init.h>
  16. #include <log.h>
  17. #include <pci.h>
  18. #include <asm/processor.h>
  19. #include <asm/immap_86xx.h>
  20. #include <asm/fsl_pci.h>
  21. #include <fsl_ddr_sdram.h>
  22. #include <asm/fsl_serdes.h>
  23. #include <linux/delay.h>
  24. #include <linux/libfdt.h>
  25. #include <fdt_support.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. long int fixed_sdram (void);
  28. int board_early_init_f (void)
  29. {
  30. return 0;
  31. }
  32. int checkboard (void)
  33. {
  34. puts ("Board: Wind River SBC8641D\n");
  35. return 0;
  36. }
  37. int dram_init(void)
  38. {
  39. long dram_size = 0;
  40. #if defined(CONFIG_SPD_EEPROM)
  41. dram_size = fsl_ddr_sdram();
  42. #else
  43. dram_size = fixed_sdram ();
  44. #endif
  45. debug(" DDR: ");
  46. gd->ram_size = dram_size;
  47. return 0;
  48. }
  49. #if defined(CONFIG_SYS_DRAM_TEST)
  50. int testdram(void)
  51. {
  52. uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  53. uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  54. uint *p;
  55. puts ("SDRAM test phase 1:\n");
  56. for (p = pstart; p < pend; p++)
  57. *p = 0xaaaaaaaa;
  58. for (p = pstart; p < pend; p++) {
  59. if (*p != 0xaaaaaaaa) {
  60. printf ("SDRAM test fails at: %08x\n", (uint) p);
  61. return 1;
  62. }
  63. }
  64. puts ("SDRAM test phase 2:\n");
  65. for (p = pstart; p < pend; p++)
  66. *p = 0x55555555;
  67. for (p = pstart; p < pend; p++) {
  68. if (*p != 0x55555555) {
  69. printf ("SDRAM test fails at: %08x\n", (uint) p);
  70. return 1;
  71. }
  72. }
  73. puts ("SDRAM test passed.\n");
  74. return 0;
  75. }
  76. #endif
  77. #if !defined(CONFIG_SPD_EEPROM)
  78. /*
  79. * Fixed sdram init -- doesn't use serial presence detect.
  80. */
  81. long int fixed_sdram (void)
  82. {
  83. #if !defined(CONFIG_SYS_RAMBOOT)
  84. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  85. volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
  86. ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  87. ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
  88. ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
  89. ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
  90. ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  91. ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
  92. ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
  93. ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
  94. ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  95. ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  96. ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  97. ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  98. ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
  99. ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
  100. ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  101. ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  102. ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
  103. ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  104. ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  105. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  106. asm ("sync;isync");
  107. udelay(500);
  108. ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
  109. asm ("sync; isync");
  110. udelay(500);
  111. ddr = &immap->im_ddr2;
  112. ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
  113. ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
  114. ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
  115. ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
  116. ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
  117. ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
  118. ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
  119. ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
  120. ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
  121. ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
  122. ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
  123. ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
  124. ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
  125. ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
  126. ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
  127. ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
  128. ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
  129. ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
  130. ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
  131. ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
  132. asm ("sync;isync");
  133. udelay(500);
  134. ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
  135. asm ("sync; isync");
  136. udelay(500);
  137. #endif
  138. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  139. }
  140. #endif /* !defined(CONFIG_SPD_EEPROM) */
  141. #if defined(CONFIG_PCI)
  142. /*
  143. * Initialize PCI Devices, report devices found.
  144. */
  145. void pci_init_board(void)
  146. {
  147. fsl_pcie_init_board(0);
  148. }
  149. #endif /* CONFIG_PCI */
  150. #if defined(CONFIG_OF_BOARD_SETUP)
  151. int ft_board_setup(void *blob, struct bd_info *bd)
  152. {
  153. ft_cpu_setup(blob, bd);
  154. FT_FSL_PCI_SETUP;
  155. return 0;
  156. }
  157. #endif
  158. void sbc8641d_reset_board (void)
  159. {
  160. puts ("Resetting board....\n");
  161. }
  162. /*
  163. * get_board_sys_clk
  164. * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
  165. */
  166. unsigned long get_board_sys_clk (ulong dummy)
  167. {
  168. int i;
  169. ulong val = 0;
  170. i = 5;
  171. i &= 0x07;
  172. switch (i) {
  173. case 0:
  174. val = 33000000;
  175. break;
  176. case 1:
  177. val = 40000000;
  178. break;
  179. case 2:
  180. val = 50000000;
  181. break;
  182. case 3:
  183. val = 66000000;
  184. break;
  185. case 4:
  186. val = 83000000;
  187. break;
  188. case 5:
  189. val = 100000000;
  190. break;
  191. case 6:
  192. val = 134000000;
  193. break;
  194. case 7:
  195. val = 166000000;
  196. break;
  197. }
  198. return val;
  199. }
  200. void board_reset(void)
  201. {
  202. #ifdef CONFIG_SYS_RESET_ADDRESS
  203. ulong addr = CONFIG_SYS_RESET_ADDRESS;
  204. /* flush and disable I/D cache */
  205. __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
  206. __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
  207. __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
  208. __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
  209. __asm__ __volatile__ ("sync");
  210. __asm__ __volatile__ ("mtspr 1008, 4");
  211. __asm__ __volatile__ ("isync");
  212. __asm__ __volatile__ ("sync");
  213. __asm__ __volatile__ ("mtspr 1008, 5");
  214. __asm__ __volatile__ ("isync");
  215. __asm__ __volatile__ ("sync");
  216. /*
  217. * SRR0 has system reset vector, SRR1 has default MSR value
  218. * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
  219. */
  220. __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
  221. __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
  222. __asm__ __volatile__ ("mtspr 27, 4");
  223. __asm__ __volatile__ ("rfi");
  224. #endif
  225. }