sbc8548.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
  4. *
  5. * Copyright 2007 Embedded Specialties, Inc.
  6. *
  7. * Copyright 2004, 2007 Freescale Semiconductor.
  8. *
  9. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  10. */
  11. #include <common.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <net.h>
  15. #include <pci.h>
  16. #include <asm/processor.h>
  17. #include <asm/immap_85xx.h>
  18. #include <asm/fsl_pci.h>
  19. #include <fsl_ddr_sdram.h>
  20. #include <asm/fsl_serdes.h>
  21. #include <spd_sdram.h>
  22. #include <netdev.h>
  23. #include <tsec.h>
  24. #include <miiphy.h>
  25. #include <linux/delay.h>
  26. #include <linux/libfdt.h>
  27. #include <fdt_support.h>
  28. void local_bus_init(void);
  29. int board_early_init_f (void)
  30. {
  31. return 0;
  32. }
  33. int checkboard (void)
  34. {
  35. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  36. volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
  37. printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
  38. in_8(rev) >> 4);
  39. /*
  40. * Initialize local bus.
  41. */
  42. local_bus_init ();
  43. out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
  44. out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
  45. return 0;
  46. }
  47. /*
  48. * Initialize Local Bus
  49. */
  50. void
  51. local_bus_init(void)
  52. {
  53. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  54. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  55. uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
  56. sys_info_t sysinfo;
  57. get_sys_info(&sysinfo);
  58. lbc_mhz = sysinfo.freq_localbus / 1000000;
  59. clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
  60. debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
  61. out_be32(&gur->lbiuiplldcr1, 0x00078080);
  62. if (clkdiv == 16) {
  63. out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
  64. } else if (clkdiv == 8) {
  65. out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
  66. } else if (clkdiv == 4) {
  67. out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
  68. }
  69. /*
  70. * Local Bus Clock > 83.3 MHz. According to timing
  71. * specifications set LCRR[EADC] to 2 delay cycles.
  72. */
  73. if (lbc_mhz > 83) {
  74. lcrr &= ~LCRR_EADC;
  75. lcrr |= LCRR_EADC_2;
  76. }
  77. /*
  78. * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
  79. * disable PLL bypass for Local Bus Clock > 83 MHz.
  80. */
  81. if (lbc_mhz >= 66)
  82. lcrr &= (~LCRR_DBYP); /* DLL Enabled */
  83. else
  84. lcrr |= LCRR_DBYP; /* DLL Bypass */
  85. out_be32(&lbc->lcrr, lcrr);
  86. asm("sync;isync;msync");
  87. /*
  88. * According to MPC8548ERMAD Rev.1.3 read back LCRR
  89. * and terminate with isync
  90. */
  91. lcrr = in_be32(&lbc->lcrr);
  92. asm ("isync;");
  93. /* let DLL stabilize */
  94. udelay(500);
  95. out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
  96. out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
  97. }
  98. /*
  99. * Initialize SDRAM memory on the Local Bus.
  100. */
  101. void lbc_sdram_init(void)
  102. {
  103. #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
  104. uint idx;
  105. const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
  106. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  107. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  108. uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
  109. puts(" SDRAM: ");
  110. print_size(size, "\n");
  111. /*
  112. * Setup SDRAM Base and Option Registers
  113. */
  114. set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
  115. set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
  116. set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
  117. set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
  118. out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
  119. asm("msync");
  120. out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
  121. out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
  122. asm("msync");
  123. /*
  124. * Issue PRECHARGE ALL command.
  125. */
  126. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
  127. asm("sync;msync");
  128. *sdram_addr = 0xff;
  129. ppcDcbf((unsigned long) sdram_addr);
  130. *sdram_addr2 = 0xff;
  131. ppcDcbf((unsigned long) sdram_addr2);
  132. udelay(100);
  133. /*
  134. * Issue 8 AUTO REFRESH commands.
  135. */
  136. for (idx = 0; idx < 8; idx++) {
  137. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
  138. asm("sync;msync");
  139. *sdram_addr = 0xff;
  140. ppcDcbf((unsigned long) sdram_addr);
  141. *sdram_addr2 = 0xff;
  142. ppcDcbf((unsigned long) sdram_addr2);
  143. udelay(100);
  144. }
  145. /*
  146. * Issue 8 MODE-set command.
  147. */
  148. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
  149. asm("sync;msync");
  150. *sdram_addr = 0xff;
  151. ppcDcbf((unsigned long) sdram_addr);
  152. *sdram_addr2 = 0xff;
  153. ppcDcbf((unsigned long) sdram_addr2);
  154. udelay(100);
  155. /*
  156. * Issue RFEN command.
  157. */
  158. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
  159. asm("sync;msync");
  160. *sdram_addr = 0xff;
  161. ppcDcbf((unsigned long) sdram_addr);
  162. *sdram_addr2 = 0xff;
  163. ppcDcbf((unsigned long) sdram_addr2);
  164. udelay(200); /* Overkill. Must wait > 200 bus cycles */
  165. #endif /* enable SDRAM init */
  166. }
  167. #if defined(CONFIG_SYS_DRAM_TEST)
  168. int
  169. testdram(void)
  170. {
  171. uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  172. uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  173. uint *p;
  174. printf("Testing DRAM from 0x%08x to 0x%08x\n",
  175. CONFIG_SYS_MEMTEST_START,
  176. CONFIG_SYS_MEMTEST_END);
  177. printf("DRAM test phase 1:\n");
  178. for (p = pstart; p < pend; p++)
  179. *p = 0xaaaaaaaa;
  180. for (p = pstart; p < pend; p++) {
  181. if (*p != 0xaaaaaaaa) {
  182. printf ("DRAM test fails at: %08x\n", (uint) p);
  183. return 1;
  184. }
  185. }
  186. printf("DRAM test phase 2:\n");
  187. for (p = pstart; p < pend; p++)
  188. *p = 0x55555555;
  189. for (p = pstart; p < pend; p++) {
  190. if (*p != 0x55555555) {
  191. printf ("DRAM test fails at: %08x\n", (uint) p);
  192. return 1;
  193. }
  194. }
  195. printf("DRAM test passed.\n");
  196. return 0;
  197. }
  198. #endif
  199. #ifdef CONFIG_PCI1
  200. static struct pci_controller pci1_hose;
  201. #endif /* CONFIG_PCI1 */
  202. #ifdef CONFIG_PCI
  203. void
  204. pci_init_board(void)
  205. {
  206. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  207. int first_free_busno = 0;
  208. #ifdef CONFIG_PCI1
  209. struct fsl_pci_info pci_info;
  210. u32 devdisr = in_be32(&gur->devdisr);
  211. u32 pordevsr = in_be32(&gur->pordevsr);
  212. u32 porpllsr = in_be32(&gur->porpllsr);
  213. if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
  214. uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
  215. uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
  216. uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
  217. uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
  218. printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
  219. (pci_32) ? 32 : 64,
  220. (pci_speed == 33000000) ? "33" :
  221. (pci_speed == 66000000) ? "66" : "unknown",
  222. pci_clk_sel ? "sync" : "async",
  223. pci_arb ? "arbiter" : "external-arbiter");
  224. SET_STD_PCI_INFO(pci_info, 1);
  225. set_next_law(pci_info.mem_phys,
  226. law_size_bits(pci_info.mem_size), pci_info.law);
  227. set_next_law(pci_info.io_phys,
  228. law_size_bits(pci_info.io_size), pci_info.law);
  229. first_free_busno = fsl_pci_init_port(&pci_info,
  230. &pci1_hose, first_free_busno);
  231. } else {
  232. printf("PCI: disabled\n");
  233. }
  234. puts("\n");
  235. #else
  236. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
  237. #endif
  238. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
  239. fsl_pcie_init_board(first_free_busno);
  240. }
  241. #endif
  242. int board_eth_init(struct bd_info *bis)
  243. {
  244. tsec_standard_init(bis);
  245. pci_eth_init(bis);
  246. return 0; /* otherwise cpu_eth_init gets run */
  247. }
  248. int last_stage_init(void)
  249. {
  250. return 0;
  251. }
  252. #if defined(CONFIG_OF_BOARD_SETUP)
  253. int ft_board_setup(void *blob, struct bd_info *bd)
  254. {
  255. ft_cpu_setup(blob, bd);
  256. #ifdef CONFIG_FSL_PCI_INIT
  257. FT_FSL_PCI_SETUP;
  258. #endif
  259. return 0;
  260. }
  261. #endif