odroid.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Samsung Electronics
  4. * Przemyslaw Marczak <p.marczak@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <asm/arch/pinmux.h>
  9. #include <asm/arch/power.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/gpio.h>
  12. #include <asm/gpio.h>
  13. #include <asm/arch/cpu.h>
  14. #include <dm.h>
  15. #include <env.h>
  16. #include <power/pmic.h>
  17. #include <power/regulator.h>
  18. #include <power/max77686_pmic.h>
  19. #include <errno.h>
  20. #include <mmc.h>
  21. #include <usb.h>
  22. #include <usb/dwc2_udc.h>
  23. #include <samsung/misc.h>
  24. #include "setup.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #ifdef CONFIG_BOARD_TYPES
  27. /* Odroid board types */
  28. enum {
  29. ODROID_TYPE_U3,
  30. ODROID_TYPE_X2,
  31. ODROID_TYPES,
  32. };
  33. void set_board_type(void)
  34. {
  35. /* Set GPA1 pin 1 to HI - enable XCL205 output */
  36. writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
  37. writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
  38. writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
  39. writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
  40. /* Set GPC1 pin 2 to IN - check XCL205 output state */
  41. writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
  42. writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
  43. /* XCL205 - needs some latch time */
  44. sdelay(200000);
  45. /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
  46. if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
  47. gd->board_type = ODROID_TYPE_X2;
  48. else
  49. gd->board_type = ODROID_TYPE_U3;
  50. }
  51. void set_board_revision(void)
  52. {
  53. /*
  54. * Revision already set by set_board_type() because it can be
  55. * executed early.
  56. */
  57. }
  58. const char *get_board_type(void)
  59. {
  60. const char *board_type[] = {"u3", "x2"};
  61. return board_type[gd->board_type];
  62. }
  63. #endif
  64. #ifdef CONFIG_SET_DFU_ALT_INFO
  65. char *get_dfu_alt_system(char *interface, char *devstr)
  66. {
  67. return env_get("dfu_alt_system");
  68. }
  69. char *get_dfu_alt_boot(char *interface, char *devstr)
  70. {
  71. struct mmc *mmc;
  72. char *alt_boot;
  73. int dev_num;
  74. dev_num = simple_strtoul(devstr, NULL, 10);
  75. mmc = find_mmc_device(dev_num);
  76. if (!mmc)
  77. return NULL;
  78. if (mmc_init(mmc))
  79. return NULL;
  80. alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
  81. CONFIG_DFU_ALT_BOOT_EMMC;
  82. return alt_boot;
  83. }
  84. #endif
  85. static void board_clock_init(void)
  86. {
  87. unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
  88. struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
  89. samsung_get_base_clock();
  90. /*
  91. * CMU_CPU clocks src to MPLL
  92. * Bit values: 0 ; 1
  93. * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
  94. * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
  95. * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
  96. * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
  97. */
  98. clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
  99. MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
  100. set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
  101. MUX_MPLL_USER_SEL_C(1);
  102. clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
  103. /* Wait for mux change */
  104. while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
  105. continue;
  106. /* Set APLL to 1000MHz */
  107. clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
  108. set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
  109. clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
  110. /* Wait for PLL to be locked */
  111. while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
  112. continue;
  113. /* Set CMU_CPU clocks src to APLL */
  114. set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
  115. MUX_MPLL_USER_SEL_C(1);
  116. clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
  117. /* Wait for mux change */
  118. while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
  119. continue;
  120. set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
  121. PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
  122. APLL_RATIO(0) | CORE2_RATIO(0);
  123. /*
  124. * Set dividers for MOUTcore = 1000 MHz
  125. * coreout = MOUT / (ratio + 1) = 1000 MHz (0)
  126. * corem0 = armclk / (ratio + 1) = 333 MHz (2)
  127. * corem1 = armclk / (ratio + 1) = 166 MHz (5)
  128. * periph = armclk / (ratio + 1) = 1000 MHz (0)
  129. * atbout = MOUT / (ratio + 1) = 200 MHz (4)
  130. * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
  131. * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
  132. * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
  133. */
  134. clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
  135. PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
  136. APLL_RATIO(7) | CORE2_RATIO(7);
  137. clrsetbits_le32(&clk->div_cpu0, clr, set);
  138. /* Wait for divider ready status */
  139. while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
  140. continue;
  141. /*
  142. * For MOUThpm = 1000 MHz (MOUTapll)
  143. * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
  144. * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
  145. * cores_out = armclk / (ratio + 1) = 200 (4)
  146. */
  147. clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
  148. set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
  149. clrsetbits_le32(&clk->div_cpu1, clr, set);
  150. /* Wait for divider ready status */
  151. while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
  152. continue;
  153. /*
  154. * Set CMU_DMC clocks src to APLL
  155. * Bit values: 0 ; 1
  156. * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
  157. * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
  158. * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
  159. * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
  160. * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
  161. * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
  162. * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
  163. * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
  164. */
  165. clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
  166. MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
  167. MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
  168. MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
  169. set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
  170. MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
  171. MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
  172. clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
  173. /* Wait for mux change */
  174. while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
  175. continue;
  176. /* Set MPLL to 800MHz */
  177. set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
  178. clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
  179. /* Wait for PLL to be locked */
  180. while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
  181. continue;
  182. /* Switch back CMU_DMC mux */
  183. set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
  184. MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
  185. MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
  186. clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
  187. /* Wait for mux change */
  188. while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
  189. continue;
  190. /* CLK_DIV_DMC0 */
  191. clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
  192. DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
  193. /*
  194. * For:
  195. * MOUTdmc = 800 MHz
  196. * MOUTdphy = 800 MHz
  197. *
  198. * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
  199. * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
  200. * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
  201. * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
  202. * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
  203. * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
  204. */
  205. set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
  206. DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
  207. clrsetbits_le32(&clk->div_dmc0, clr, set);
  208. /* Wait for divider ready status */
  209. while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
  210. continue;
  211. /* CLK_DIV_DMC1 */
  212. clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
  213. C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
  214. /*
  215. * For:
  216. * MOUTg2d = 800 MHz
  217. * MOUTc2c = 800 Mhz
  218. * MOUTpwi = 108 MHz
  219. *
  220. * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
  221. * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
  222. * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
  223. * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
  224. */
  225. set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
  226. C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
  227. clrsetbits_le32(&clk->div_dmc1, clr, set);
  228. /* Wait for divider ready status */
  229. while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
  230. continue;
  231. /* CLK_SRC_PERIL0 */
  232. clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
  233. UART3_SEL(15) | UART4_SEL(15);
  234. /*
  235. * Set CLK_SRC_PERIL0 clocks src to MPLL
  236. * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
  237. * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
  238. * 8(SCLK_VPLL)
  239. *
  240. * Set all to SCLK_MPLL_USER_T
  241. */
  242. set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
  243. UART4_SEL(6);
  244. clrsetbits_le32(&clk->src_peril0, clr, set);
  245. /* CLK_DIV_PERIL0 */
  246. clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
  247. UART3_RATIO(15) | UART4_RATIO(15);
  248. /*
  249. * For MOUTuart0-4: 800MHz
  250. *
  251. * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
  252. */
  253. set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
  254. UART3_RATIO(7) | UART4_RATIO(7);
  255. clrsetbits_le32(&clk->div_peril0, clr, set);
  256. while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
  257. continue;
  258. /* CLK_DIV_FSYS1 */
  259. clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
  260. MMC1_PRE_RATIO(255);
  261. /*
  262. * For MOUTmmc0-3 = 800 MHz (MPLL)
  263. *
  264. * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
  265. * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
  266. * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
  267. * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
  268. */
  269. set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
  270. MMC1_PRE_RATIO(1);
  271. clrsetbits_le32(&clk->div_fsys1, clr, set);
  272. /* Wait for divider ready status */
  273. while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
  274. continue;
  275. /* CLK_DIV_FSYS2 */
  276. clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
  277. MMC3_PRE_RATIO(255);
  278. /*
  279. * For MOUTmmc0-3 = 800 MHz (MPLL)
  280. *
  281. * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
  282. * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
  283. * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
  284. * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
  285. */
  286. set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
  287. MMC3_PRE_RATIO(1);
  288. clrsetbits_le32(&clk->div_fsys2, clr, set);
  289. /* Wait for divider ready status */
  290. while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
  291. continue;
  292. /* CLK_DIV_FSYS3 */
  293. clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
  294. /*
  295. * For MOUTmmc4 = 800 MHz (MPLL)
  296. *
  297. * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
  298. * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
  299. */
  300. set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
  301. clrsetbits_le32(&clk->div_fsys3, clr, set);
  302. /* Wait for divider ready status */
  303. while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
  304. continue;
  305. return;
  306. }
  307. static void board_gpio_init(void)
  308. {
  309. /* eMMC Reset Pin */
  310. gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
  311. gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
  312. gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
  313. gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
  314. /* Enable FAN (Odroid U3) */
  315. gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
  316. gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
  317. gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
  318. gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
  319. /* OTG Vbus output (Odroid U3+) */
  320. gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
  321. gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
  322. gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
  323. gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
  324. /* OTG INT (Odroid U3+) */
  325. gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
  326. gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
  327. gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
  328. gpio_direction_input(EXYNOS4X12_GPIO_X31);
  329. /* Blue LED (Odroid X2/U2/U3) */
  330. gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
  331. gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
  332. #ifdef CONFIG_CMD_USB
  333. /* USB3503A Reference frequency */
  334. gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
  335. /* USB3503A Connect */
  336. gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
  337. /* USB3503A Reset */
  338. gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
  339. #endif
  340. }
  341. int exynos_early_init_f(void)
  342. {
  343. board_clock_init();
  344. return 0;
  345. }
  346. int exynos_init(void)
  347. {
  348. board_gpio_init();
  349. return 0;
  350. }
  351. int exynos_power_init(void)
  352. {
  353. const char *mmc_regulators[] = {
  354. "VDDQ_EMMC_1.8V",
  355. "VDDQ_EMMC_2.8V",
  356. "TFLASH_2.8V",
  357. NULL,
  358. };
  359. if (regulator_list_autoset(mmc_regulators, NULL, true))
  360. pr_err("Unable to init all mmc regulators\n");
  361. return 0;
  362. }
  363. #ifdef CONFIG_USB_GADGET
  364. static int s5pc210_phy_control(int on)
  365. {
  366. struct udevice *dev;
  367. int ret;
  368. ret = regulator_get_by_platname("VDD_UOTG_3.0V", &dev);
  369. if (ret) {
  370. pr_err("Regulator get error: %d\n", ret);
  371. return ret;
  372. }
  373. if (on)
  374. return regulator_set_mode(dev, OPMODE_ON);
  375. else
  376. return regulator_set_mode(dev, OPMODE_LPM);
  377. }
  378. struct dwc2_plat_otg_data s5pc210_otg_data = {
  379. .phy_control = s5pc210_phy_control,
  380. .regs_phy = EXYNOS4X12_USBPHY_BASE,
  381. .regs_otg = EXYNOS4X12_USBOTG_BASE,
  382. .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
  383. .usb_flags = PHY0_SLEEP,
  384. };
  385. #endif
  386. #if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
  387. static void set_usb3503_ref_clk(void)
  388. {
  389. #ifdef CONFIG_BOARD_TYPES
  390. /*
  391. * gpx3-0 chooses primary (low) or secondary (high) reference clock
  392. * frequencies table. The choice of clock is done through hard-wired
  393. * REF_SEL pins.
  394. * The Odroid Us have reference clock at 24 MHz (00 entry from secondary
  395. * table) and Odroid Xs have it at 26 MHz (01 entry from primary table).
  396. */
  397. if (gd->board_type == ODROID_TYPE_U3)
  398. gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
  399. else
  400. gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
  401. #else
  402. /* Choose Odroid Xs frequency without board types */
  403. gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
  404. #endif /* CONFIG_BOARD_TYPES */
  405. }
  406. int board_usb_init(int index, enum usb_init_type init)
  407. {
  408. #ifdef CONFIG_CMD_USB
  409. struct udevice *dev;
  410. int ret;
  411. set_usb3503_ref_clk();
  412. /* Disconnect, Reset, Connect */
  413. gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
  414. gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
  415. gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
  416. gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
  417. /* Power off and on BUCK8 for LAN9730 */
  418. debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
  419. ret = regulator_get_by_platname("VCC_P3V3_2.85V", &dev);
  420. if (ret) {
  421. pr_err("Regulator get error: %d\n", ret);
  422. return ret;
  423. }
  424. ret = regulator_set_enable(dev, true);
  425. if (ret) {
  426. pr_err("Regulator %s enable setting error: %d\n", dev->name, ret);
  427. return ret;
  428. }
  429. ret = regulator_set_value(dev, 750000);
  430. if (ret) {
  431. pr_err("Regulator %s value setting error: %d\n", dev->name, ret);
  432. return ret;
  433. }
  434. ret = regulator_set_value(dev, 3300000);
  435. if (ret) {
  436. pr_err("Regulator %s value setting error: %d\n", dev->name, ret);
  437. return ret;
  438. }
  439. #endif
  440. debug("USB_udc_probe\n");
  441. return dwc2_udc_probe(&s5pc210_otg_data);
  442. }
  443. #endif