lowlevel_init.S 2.6 KB

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  1. /*
  2. * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
  3. * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
  4. * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  5. */
  6. #include <config.h>
  7. #include <asm/processor.h>
  8. #include <asm/macro.h>
  9. .global lowlevel_init
  10. .text
  11. .align 2
  12. lowlevel_init:
  13. write32 CCR_A, CCR_D_D
  14. write32 MMUCR_A, MMUCR_D
  15. write32 BCR1_A, BCR1_D
  16. write16 BCR2_A, BCR2_D
  17. write16 BCR3_A, BCR3_D
  18. write32 BCR4_A, BCR4_D
  19. write32 WCR1_A, WCR1_D
  20. write32 WCR2_A, WCR2_D
  21. write32 WCR3_A, WCR3_D
  22. write16 PCR_A, PCR_D
  23. write16 LED_A, LED_D
  24. write32 MCR_A, MCR_D1
  25. write16 RTCNT_A, RTCNT_D
  26. write16 RTCOR_A, RTCOR_D
  27. write16 RFCR_A, RFCR_D
  28. write16 RTCSR_A, RTCSR_D
  29. write8 SDMR3_A, SDMR3_D0
  30. /* Wait DRAM refresh 30 times */
  31. mov.l RFCR_A, r1
  32. mov #30, r3
  33. 1:
  34. mov.w @r1, r0
  35. extu.w r0, r2
  36. cmp/hi r3, r2
  37. bf 1b
  38. write32 MCR_A, MCR_D2
  39. write8 SDMR3_A, SDMR3_D1
  40. write32 IRLMASK_A, IRLMASK_D
  41. write32 CCR_A, CCR_D_E
  42. rts
  43. nop
  44. .align 2
  45. CCR_A: .long CCR /* Cache Control Register */
  46. CCR_D_D: .long 0x0808 /* Flush the cache, disable */
  47. CCR_D_E: .long 0x8000090B
  48. FRQCR_A: .long FRQCR /* FRQCR Address */
  49. FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
  50. BCR1_A: .long BCR1 /* BCR1 Address */
  51. BCR1_D: .long 0x00180008
  52. BCR2_A: .long BCR2 /* BCR2 Address */
  53. BCR2_D: .long 0xabe8
  54. BCR3_A: .long BCR3 /* BCR3 Address */
  55. BCR3_D: .long 0x0000
  56. BCR4_A: .long BCR4 /* BCR4 Address */
  57. BCR4_D: .long 0x00000010
  58. WCR1_A: .long WCR1 /* WCR1 Address */
  59. WCR1_D: .long 0x33343333
  60. WCR2_A: .long WCR2 /* WCR2 Address */
  61. WCR2_D: .long 0xcff86fbf
  62. WCR3_A: .long WCR3 /* WCR3 Address */
  63. WCR3_D: .long 0x07777707
  64. LED_A: .long 0x04000036 /* LED Address */
  65. LED_D: .long 0xFF /* LED Data */
  66. RTCNT_A: .long RTCNT /* RTCNT Address */
  67. RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
  68. .align 2
  69. RTCOR_A: .long RTCOR /* RTCOR Address */
  70. RTCOR_D: .word 0xA534 /* RTCOR Write Code */
  71. .align 2
  72. RTCSR_A: .long RTCSR /* RTCSR Address */
  73. RTCSR_D: .word 0xA510 /* RTCSR Write Code */
  74. .align 2
  75. SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
  76. SDMR3_D0: .long 0x55
  77. SDMR3_D1: .long 0x00
  78. MCR_A: .long MCR /* MCR Address */
  79. MCR_D1: .long 0x081901F4 /* MRSET:'0' */
  80. MCR_D2: .long 0x481901F4 /* MRSET:'1' */
  81. RFCR_A: .long RFCR /* RFCR Address */
  82. RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
  83. PCR_A: .long PCR /* PCR Address */
  84. PCR_D: .long 0x0000
  85. MMUCR_A: .long MMUCR /* MMUCCR Address */
  86. MMUCR_D: .long 0x00000000 /* MMUCCR Data */
  87. IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */
  88. IRLMASK_D: .long 0x00000000 /* IRLMASK Data */