lowlevel_init.S 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2017 Renesas Electronics
  4. * Copyright (C) 2017 Chris Brandt
  5. */
  6. #include <config.h>
  7. #include <version.h>
  8. #include <asm/macro.h>
  9. /* Watchdog Registers */
  10. #define RZA1_WDT_BASE 0xFCFE0000
  11. #define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */
  12. #define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */
  13. #define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */
  14. /* Standby controller registers (chapter 55) */
  15. #define RZA1_STBCR_BASE 0xFCFE0020
  16. #define STBCR1 (RZA1_STBCR_BASE + 0x00)
  17. #define STBCR2 (RZA1_STBCR_BASE + 0x04)
  18. #define STBCR3 (RZA1_STBCR_BASE + 0x400)
  19. #define STBCR4 (RZA1_STBCR_BASE + 0x404)
  20. #define STBCR5 (RZA1_STBCR_BASE + 0x408)
  21. #define STBCR6 (RZA1_STBCR_BASE + 0x40c)
  22. #define STBCR7 (RZA1_STBCR_BASE + 0x410)
  23. #define STBCR8 (RZA1_STBCR_BASE + 0x414)
  24. #define STBCR9 (RZA1_STBCR_BASE + 0x418)
  25. #define STBCR10 (RZA1_STBCR_BASE + 0x41c)
  26. #define STBCR11 (RZA1_STBCR_BASE + 0x420)
  27. #define STBCR12 (RZA1_STBCR_BASE + 0x424)
  28. #define STBCR13 (RZA1_STBCR_BASE + 0x450)
  29. /* Clock Registers */
  30. #define RZA1_FRQCR_BASE 0xFCFE0010
  31. #define FRQCR (RZA1_FRQCR_BASE + 0x00)
  32. #define FRQCR2 (RZA1_FRQCR_BASE + 0x04)
  33. #define SYSCR1 0xFCFE0400 /* System control register 1 */
  34. #define SYSCR2 0xFCFE0404 /* System control register 2 */
  35. #define SYSCR3 0xFCFE0408 /* System control register 3 */
  36. /* Disable WDT */
  37. #define WTCSR_D 0xA518
  38. #define WTCNT_D 0x5A00
  39. /* Enable all peripheral clocks */
  40. #define STBCR3_D 0x00000000
  41. #define STBCR4_D 0x00000000
  42. #define STBCR5_D 0x00000000
  43. #define STBCR6_D 0x00000000
  44. #define STBCR7_D 0x00000024
  45. #define STBCR8_D 0x00000005
  46. #define STBCR9_D 0x00000000
  47. #define STBCR10_D 0x00000000
  48. #define STBCR11_D 0x000000c0
  49. #define STBCR12_D 0x000000f0
  50. /*
  51. * Set all system clocks to full speed.
  52. * On reset, the CPU will be running at 1/2 speed.
  53. * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges
  54. */
  55. #define FRQCR_D 0x0035
  56. #define FRQCR2_D 0x0001
  57. .global lowlevel_init
  58. .text
  59. .align 2
  60. lowlevel_init:
  61. /* PL310 init */
  62. write32 0x3fffff80, 0x00000001
  63. /* Disable WDT */
  64. write16 WTCSR, WTCSR_D
  65. write16 WTCNT, WTCNT_D
  66. /* Set clocks */
  67. write16 FRQCR, FRQCR_D
  68. write16 FRQCR2, FRQCR2_D
  69. /* Enable all peripherals(Standby Control) */
  70. write8 STBCR3, STBCR3_D
  71. write8 STBCR4, STBCR4_D
  72. write8 STBCR5, STBCR5_D
  73. write8 STBCR6, STBCR6_D
  74. write8 STBCR7, STBCR7_D
  75. write8 STBCR8, STBCR8_D
  76. write8 STBCR9, STBCR9_D
  77. write8 STBCR10, STBCR10_D
  78. write8 STBCR11, STBCR11_D
  79. write8 STBCR12, STBCR12_D
  80. /* For serial booting, enable read ahead caching to speed things up */
  81. #define DRCR_0 0x3FEFA00C
  82. write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */
  83. /* Enable all internal RAM */
  84. write8 SYSCR1, 0xFF
  85. write8 SYSCR2, 0xFF
  86. write8 SYSCR3, 0xFF
  87. nop
  88. /* back to arch calling code */
  89. mov pc, lr
  90. .align 4