gose.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/gose/gose.c
  4. *
  5. * Copyright (C) 2014 Renesas Electronics Corporation
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <hang.h>
  11. #include <init.h>
  12. #include <malloc.h>
  13. #include <dm.h>
  14. #include <dm/platform_data/serial_sh.h>
  15. #include <env_internal.h>
  16. #include <asm/processor.h>
  17. #include <asm/mach-types.h>
  18. #include <asm/io.h>
  19. #include <linux/bitops.h>
  20. #include <linux/delay.h>
  21. #include <linux/errno.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/gpio.h>
  24. #include <asm/arch/rmobile.h>
  25. #include <asm/arch/rcar-mstp.h>
  26. #include <asm/arch/sh_sdhi.h>
  27. #include <netdev.h>
  28. #include <miiphy.h>
  29. #include <i2c.h>
  30. #include "qos.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #define CLK2MHZ(clk) (clk / 1000 / 1000)
  33. void s_init(void)
  34. {
  35. struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  36. struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  37. u32 stc;
  38. /* Watchdog init */
  39. writel(0xA5A5A500, &rwdt->rwtcsra);
  40. writel(0xA5A5A500, &swdt->swtcsra);
  41. /* CPU frequency setting. Set to 1.5GHz */
  42. stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
  43. clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  44. /* QoS */
  45. qos_init();
  46. }
  47. #define TMU0_MSTP125 BIT(25)
  48. #define SD1CKCR 0xE6150078
  49. #define SD2CKCR 0xE615026C
  50. #define SD_97500KHZ 0x7
  51. int board_early_init_f(void)
  52. {
  53. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  54. /*
  55. * SD0 clock is set to 97.5MHz by default.
  56. * Set SD1 and SD2 to the 97.5MHz as well.
  57. */
  58. writel(SD_97500KHZ, SD1CKCR);
  59. writel(SD_97500KHZ, SD2CKCR);
  60. return 0;
  61. }
  62. #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
  63. int board_init(void)
  64. {
  65. /* adress of boot parameters */
  66. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  67. /* Force ethernet PHY out of reset */
  68. gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  69. gpio_direction_output(ETHERNET_PHY_RESET, 0);
  70. mdelay(10);
  71. gpio_direction_output(ETHERNET_PHY_RESET, 1);
  72. return 0;
  73. }
  74. int dram_init(void)
  75. {
  76. if (fdtdec_setup_mem_size_base() != 0)
  77. return -EINVAL;
  78. return 0;
  79. }
  80. int dram_init_banksize(void)
  81. {
  82. fdtdec_setup_memory_banksize();
  83. return 0;
  84. }
  85. /* KSZ8041RNLI */
  86. #define PHY_CONTROL1 0x1E
  87. #define PHY_LED_MODE 0xC000
  88. #define PHY_LED_MODE_ACK 0x4000
  89. int board_phy_config(struct phy_device *phydev)
  90. {
  91. int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
  92. ret &= ~PHY_LED_MODE;
  93. ret |= PHY_LED_MODE_ACK;
  94. ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
  95. return 0;
  96. }
  97. void reset_cpu(ulong addr)
  98. {
  99. struct udevice *dev;
  100. const u8 pmic_bus = 6;
  101. const u8 pmic_addr = 0x58;
  102. u8 data;
  103. int ret;
  104. ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
  105. if (ret)
  106. hang();
  107. ret = dm_i2c_read(dev, 0x13, &data, 1);
  108. if (ret)
  109. hang();
  110. data |= BIT(1);
  111. ret = dm_i2c_write(dev, 0x13, &data, 1);
  112. if (ret)
  113. hang();
  114. }
  115. enum env_location env_get_location(enum env_operation op, int prio)
  116. {
  117. const u32 load_magic = 0xb33fc0de;
  118. /* Block environment access if loaded using JTAG */
  119. if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
  120. (op != ENVOP_INIT))
  121. return ENVL_UNKNOWN;
  122. if (prio)
  123. return ENVL_UNKNOWN;
  124. return ENVL_SPI_FLASH;
  125. }