maxbcm.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <miiphy.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/cpu.h>
  10. #include <asm/arch/soc.h>
  11. #include <linux/mbus.h>
  12. #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
  13. #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
  14. DECLARE_GLOBAL_DATA_PTR;
  15. /* Base addresses for the external device chip selects */
  16. #define DEV_CS0_BASE 0xe0000000
  17. #define DEV_CS1_BASE 0xe1000000
  18. #define DEV_CS2_BASE 0xe2000000
  19. #define DEV_CS3_BASE 0xe3000000
  20. /* DDR3 static configuration */
  21. MV_DRAM_MC_INIT ddr3_b0_maxbcm[MV_MAX_DDR3_STATIC_SIZE] = {
  22. {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */
  23. {0x00001404, 0x30000820}, /* Dunit Control Low Register */
  24. {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */
  25. {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */
  26. {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */
  27. {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */
  28. {0x00001418, 0x00000e00}, /* DDR SDRAM Operation Register */
  29. {0x0000141C, 0x00000672}, /* DDR SDRAM Mode Register */
  30. {0x00001420, 0x00000004}, /* DDR SDRAM Extended Mode Register */
  31. {0x00001424, 0x0000F3FF}, /* Dunit Control High Register */
  32. {0x00001428, 0x0011A940}, /* Dunit Control High Register */
  33. {0x0000142C, 0x014C5134}, /* Dunit Control High Register */
  34. {0x0000147C, 0x0000D771},
  35. {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
  36. {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
  37. {0x000014A0, 0x00000001},
  38. {0x000014A8, 0x00000101},
  39. /* Recommended Settings from Marvell for 4 x 16 bit devices: */
  40. {0x000014C0, 0x192424C9}, /* DRAM addr and Ctrl Driving Strenght*/
  41. {0x000014C4, 0xAAA24C9}, /* DRAM Data and DQS Driving Strenght */
  42. /*
  43. * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
  44. * training sequence
  45. */
  46. {0x000200e8, 0x3FFF0E01},
  47. {0x00020184, 0x3FFFFFE0}, /* Close fast path Window to - 2G */
  48. {0x0001504, 0x3FFFFFE1}, /* CS0 Size */
  49. {0x000150C, 0x00000000}, /* CS1 Size */
  50. {0x0001514, 0x00000000}, /* CS2 Size */
  51. {0x000151C, 0x00000000}, /* CS3 Size */
  52. {0x0020220, 0x00000007}, /* Reserved */
  53. {0x00001538, 0x0000000B}, /* Read Data Sample Delays Register */
  54. {0x0000153C, 0x0000000B}, /* Read Data Ready Delay Register */
  55. {0x000015D0, 0x00000670}, /* MR0 */
  56. {0x000015D4, 0x00000044}, /* MR1 */
  57. {0x000015D8, 0x00000018}, /* MR2 */
  58. {0x000015DC, 0x00000000}, /* MR3 */
  59. {0x000015E0, 0x00000001},
  60. {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
  61. {0x000015EC, 0xF800A225}, /* DDR PHY */
  62. {0x0, 0x0}
  63. };
  64. MV_DRAM_MODES maxbcm_ddr_modes[MV_DDR3_MODES_NUMBER] = {
  65. {"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL},
  66. };
  67. extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
  68. /* MAXBCM: SERDES 0-4 PCIE, Serdes 7 = SGMII 0, all others = unconnected */
  69. MV_BIN_SERDES_CFG maxbcm_serdes_cfg[] = {
  70. { MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000,
  71. { PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
  72. PEX_BUS_DISABLED },
  73. 0x1f, serdes_change_m_phy
  74. }
  75. };
  76. MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
  77. {
  78. /* Only one mode supported for this board */
  79. return &maxbcm_ddr_modes[0];
  80. }
  81. MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
  82. {
  83. return &maxbcm_serdes_cfg[0];
  84. }
  85. int board_early_init_f(void)
  86. {
  87. /*
  88. * Don't configure MPP (pin multiplexing) and GPIO here,
  89. * its already done in bin_hdr
  90. */
  91. /*
  92. * Setup some board specific mbus address windows
  93. */
  94. mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20,
  95. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0);
  96. mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20,
  97. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
  98. mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20,
  99. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2);
  100. mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20,
  101. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3);
  102. return 0;
  103. }
  104. int board_init(void)
  105. {
  106. /* adress of boot parameters */
  107. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  108. return 0;
  109. }
  110. int checkboard(void)
  111. {
  112. puts("Board: maxBCM\n");
  113. return 0;
  114. }
  115. /* Configure and enable MV88E6185 switch */
  116. int board_phy_config(struct phy_device *phydev)
  117. {
  118. /*
  119. * todo:
  120. * Fill this with the real setup / config code.
  121. * Please see board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
  122. * for details.
  123. */
  124. printf("88E6185 Initialized\n");
  125. return 0;
  126. }