wb50n.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. */
  4. #include <common.h>
  5. #include <init.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/at91_sfr.h>
  8. #include <asm/arch/sama5d3_smc.h>
  9. #include <asm/arch/at91_common.h>
  10. #include <asm/arch/at91_pmc.h>
  11. #include <asm/arch/at91_rstc.h>
  12. #include <asm/arch/gpio.h>
  13. #include <asm/arch/clk.h>
  14. #include <env.h>
  15. #include <micrel.h>
  16. #include <net.h>
  17. #include <netdev.h>
  18. #include <spl.h>
  19. #include <asm/arch/atmel_mpddrc.h>
  20. #include <asm/arch/at91_wdt.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /* ------------------------------------------------------------------------- */
  23. /*
  24. * Miscelaneous platform dependent initialisations
  25. */
  26. void wb50n_nand_hw_init(void)
  27. {
  28. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  29. at91_periph_clk_enable(ATMEL_ID_SMC);
  30. /* Configure SMC CS3 for NAND/SmartMedia */
  31. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  32. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  33. &smc->cs[3].setup);
  34. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  35. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  36. &smc->cs[3].pulse);
  37. writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  38. &smc->cs[3].cycle);
  39. writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  40. AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
  41. AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) |
  42. AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  43. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  44. AT91_SMC_MODE_EXNW_DISABLE |
  45. AT91_SMC_MODE_DBW_8 |
  46. AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode);
  47. /* Disable Flash Write Protect Line */
  48. at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
  49. }
  50. int board_early_init_f(void)
  51. {
  52. at91_periph_clk_enable(ATMEL_ID_PIOA);
  53. at91_periph_clk_enable(ATMEL_ID_PIOB);
  54. at91_periph_clk_enable(ATMEL_ID_PIOC);
  55. at91_periph_clk_enable(ATMEL_ID_PIOD);
  56. at91_periph_clk_enable(ATMEL_ID_PIOE);
  57. at91_seriald_hw_init();
  58. return 0;
  59. }
  60. int board_init(void)
  61. {
  62. /* adress of boot parameters */
  63. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  64. wb50n_nand_hw_init();
  65. at91_macb_hw_init();
  66. return 0;
  67. }
  68. int dram_init(void)
  69. {
  70. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  71. CONFIG_SYS_SDRAM_SIZE);
  72. return 0;
  73. }
  74. int board_phy_config(struct phy_device *phydev)
  75. {
  76. /* rx data delay */
  77. ksz9021_phy_extended_write(phydev,
  78. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
  79. /* tx data delay */
  80. ksz9021_phy_extended_write(phydev,
  81. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
  82. /* rx/tx clock delay */
  83. ksz9021_phy_extended_write(phydev,
  84. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
  85. return 0;
  86. }
  87. int board_eth_init(struct bd_info *bis)
  88. {
  89. int rc = 0;
  90. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
  91. return rc;
  92. }
  93. #ifdef CONFIG_BOARD_LATE_INIT
  94. #include <linux/ctype.h>
  95. int board_late_init(void)
  96. {
  97. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  98. const char *LAIRD_NAME = "lrd_name";
  99. char name[32], *p;
  100. strcpy(name, get_cpu_name());
  101. for (p = name; *p != '\0'; *p = tolower(*p), p++)
  102. ;
  103. strcat(name, "-wb50n");
  104. env_set(LAIRD_NAME, name);
  105. #endif
  106. return 0;
  107. }
  108. #endif
  109. /* SPL */
  110. #ifdef CONFIG_SPL_BUILD
  111. void spl_board_init(void)
  112. {
  113. wb50n_nand_hw_init();
  114. }
  115. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  116. {
  117. ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
  118. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
  119. ATMEL_MPDDRC_CR_NR_ROW_13 |
  120. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  121. ATMEL_MPDDRC_CR_NDQS_DISABLED |
  122. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  123. ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
  124. ddr2->rtr = 0x411;
  125. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  126. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  127. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  128. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  129. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  130. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  131. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  132. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  133. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  134. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  135. 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  136. 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  137. ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
  138. 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  139. 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  140. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  141. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  142. }
  143. void mem_init(void)
  144. {
  145. struct atmel_mpddrc_config ddr2;
  146. ddr2_conf(&ddr2);
  147. configure_ddrcfg_input_buffers(true);
  148. /* enable MPDDR clock */
  149. at91_periph_clk_enable(ATMEL_ID_MPDDRC);
  150. at91_system_clk_enable(AT91_PMC_DDR);
  151. /* DDRAM2 Controller initialize */
  152. ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
  153. }
  154. void at91_pmc_init(void)
  155. {
  156. u32 tmp;
  157. tmp = AT91_PMC_PLLAR_29 |
  158. AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
  159. AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1);
  160. at91_plla_init(tmp);
  161. at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
  162. tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA;
  163. at91_mck_init(tmp);
  164. }
  165. #endif