video.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Novena video output support
  4. *
  5. * IT6251 code based on code Copyright (C) 2014 Sean Cross
  6. * from https://github.com/xobs/novena-linux.git commit
  7. * 3d85836ee1377d445531928361809612aa0a18db
  8. *
  9. * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  10. */
  11. #include <common.h>
  12. #include <log.h>
  13. #include <linux/delay.h>
  14. #include <linux/errno.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/crm_regs.h>
  19. #include <asm/arch/imx-regs.h>
  20. #include <asm/arch/iomux.h>
  21. #include <asm/arch/mxc_hdmi.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/mach-imx/iomux-v3.h>
  24. #include <asm/mach-imx/mxc_i2c.h>
  25. #include <asm/mach-imx/video.h>
  26. #include <i2c.h>
  27. #include <input.h>
  28. #include <ipu_pixfmt.h>
  29. #include <linux/fb.h>
  30. #include <linux/input.h>
  31. #include <malloc.h>
  32. #include <stdio_dev.h>
  33. #include "novena.h"
  34. #define IT6251_VENDOR_ID_LOW 0x00
  35. #define IT6251_VENDOR_ID_HIGH 0x01
  36. #define IT6251_DEVICE_ID_LOW 0x02
  37. #define IT6251_DEVICE_ID_HIGH 0x03
  38. #define IT6251_SYSTEM_STATUS 0x0d
  39. #define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0)
  40. #define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1)
  41. #define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2)
  42. #define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3)
  43. #define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4)
  44. #define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5)
  45. #define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6)
  46. #define IT6251_REF_STATE 0x0e
  47. #define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0)
  48. #define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1)
  49. #define IT6251_REF_STATE_CR_PATTERN (1 << 2)
  50. #define IT6251_REF_STATE_EQ_PATTERN (1 << 3)
  51. #define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4)
  52. #define IT6251_REF_STATE_MUTED (1 << 5)
  53. #define IT6251_REG_PCLK_CNT_LOW 0x57
  54. #define IT6251_REG_PCLK_CNT_HIGH 0x58
  55. #define IT6521_RETRY_MAX 20
  56. static int it6251_is_stable(void)
  57. {
  58. const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
  59. const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
  60. int status;
  61. int clkcnt;
  62. int rpclkcnt;
  63. int refstate;
  64. rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
  65. ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
  66. debug("RPCLKCnt: %d\n", rpclkcnt);
  67. status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
  68. debug("System status: 0x%02x\n", status);
  69. clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
  70. ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
  71. 0x0f00);
  72. debug("Clock: 0x%02x\n", clkcnt);
  73. refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
  74. debug("Ref Link State: 0x%02x\n", refstate);
  75. if ((refstate & 0x1f) != 0)
  76. return 0;
  77. /* If video is muted, that's a failure */
  78. if (refstate & IT6251_REF_STATE_MUTED)
  79. return 0;
  80. if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
  81. return 0;
  82. return 1;
  83. }
  84. static int it6251_ready(void)
  85. {
  86. const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
  87. /* Test if the IT6251 came out of reset by reading ID regs. */
  88. if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
  89. return 0;
  90. if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
  91. return 0;
  92. if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
  93. return 0;
  94. if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
  95. return 0;
  96. return 1;
  97. }
  98. static void it6251_program_regs(void)
  99. {
  100. const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
  101. const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
  102. i2c_reg_write(caddr, 0x05, 0x00);
  103. mdelay(1);
  104. /* set LVDSRX address, and enable */
  105. i2c_reg_write(caddr, 0xfd, 0xbc);
  106. i2c_reg_write(caddr, 0xfe, 0x01);
  107. /*
  108. * LVDSRX
  109. */
  110. /* This write always fails, because the chip goes into reset */
  111. /* reset LVDSRX */
  112. i2c_reg_write(laddr, 0x05, 0xff);
  113. i2c_reg_write(laddr, 0x05, 0x00);
  114. /* reset LVDSRX PLL */
  115. i2c_reg_write(laddr, 0x3b, 0x42);
  116. i2c_reg_write(laddr, 0x3b, 0x43);
  117. /* something with SSC PLL */
  118. i2c_reg_write(laddr, 0x3c, 0x08);
  119. /* don't swap links, but writing reserved registers */
  120. i2c_reg_write(laddr, 0x0b, 0x88);
  121. /* JEIDA, 8-bit depth 0x11, orig 0x42 */
  122. i2c_reg_write(laddr, 0x2c, 0x01);
  123. /* "reserved" */
  124. i2c_reg_write(laddr, 0x32, 0x04);
  125. /* "reserved" */
  126. i2c_reg_write(laddr, 0x35, 0xe0);
  127. /* "reserved" + clock delay */
  128. i2c_reg_write(laddr, 0x2b, 0x24);
  129. /* reset LVDSRX pix clock */
  130. i2c_reg_write(laddr, 0x05, 0x02);
  131. i2c_reg_write(laddr, 0x05, 0x00);
  132. /*
  133. * DPTX
  134. */
  135. /* set for two lane mode, normal op, no swapping, no downspread */
  136. i2c_reg_write(caddr, 0x16, 0x02);
  137. /* some AUX channel EDID magic */
  138. i2c_reg_write(caddr, 0x23, 0x40);
  139. /* power down lanes 3-0 */
  140. i2c_reg_write(caddr, 0x5c, 0xf3);
  141. /* enable DP scrambling, change EQ CR phase */
  142. i2c_reg_write(caddr, 0x5f, 0x06);
  143. /* color mode RGB, pclk/2 */
  144. i2c_reg_write(caddr, 0x60, 0x02);
  145. /* dual pixel input mode, no EO swap, no RGB swap */
  146. i2c_reg_write(caddr, 0x61, 0x04);
  147. /* M444B24 video format */
  148. i2c_reg_write(caddr, 0x62, 0x01);
  149. /* vesa range / not interlace / vsync high / hsync high */
  150. i2c_reg_write(caddr, 0xa0, 0x0F);
  151. /* hpd event timer set to 1.6-ish ms */
  152. i2c_reg_write(caddr, 0xc9, 0xf5);
  153. /* more reserved magic */
  154. i2c_reg_write(caddr, 0xca, 0x4d);
  155. i2c_reg_write(caddr, 0xcb, 0x37);
  156. /* enhanced framing mode, auto video fifo reset, video mute disable */
  157. i2c_reg_write(caddr, 0xd3, 0x03);
  158. /* "vidstmp" and some reserved stuff */
  159. i2c_reg_write(caddr, 0xd4, 0x45);
  160. /* queue number -- reserved */
  161. i2c_reg_write(caddr, 0xe7, 0xa0);
  162. /* info frame packets and reserved */
  163. i2c_reg_write(caddr, 0xe8, 0x33);
  164. /* more AVI stuff */
  165. i2c_reg_write(caddr, 0xec, 0x00);
  166. /* select PC master reg for aux channel? */
  167. i2c_reg_write(caddr, 0x23, 0x42);
  168. /* send PC request commands */
  169. i2c_reg_write(caddr, 0x24, 0x00);
  170. i2c_reg_write(caddr, 0x25, 0x00);
  171. i2c_reg_write(caddr, 0x26, 0x00);
  172. /* native aux read */
  173. i2c_reg_write(caddr, 0x2b, 0x00);
  174. /* back to internal */
  175. i2c_reg_write(caddr, 0x23, 0x40);
  176. /* voltage swing level 3 */
  177. i2c_reg_write(caddr, 0x19, 0xff);
  178. /* pre-emphasis level 3 */
  179. i2c_reg_write(caddr, 0x1a, 0xff);
  180. /* start link training */
  181. i2c_reg_write(caddr, 0x17, 0x01);
  182. }
  183. static int it6251_init(void)
  184. {
  185. const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
  186. int reg;
  187. int tries, retries = 0;
  188. for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
  189. /* Program the chip. */
  190. it6251_program_regs();
  191. /* Wait for video stable. */
  192. for (tries = 0; tries < 100; tries++) {
  193. reg = i2c_reg_read(caddr, 0x17);
  194. /* Test Link CFG, STS, LCS read done. */
  195. if ((reg & 0xe0) != 0xe0) {
  196. /* Not yet, wait a bit more. */
  197. mdelay(2);
  198. continue;
  199. }
  200. /* Test if the video input is stable. */
  201. if (it6251_is_stable())
  202. return 0;
  203. }
  204. /*
  205. * If we couldn't stabilize, requeue and try again,
  206. * because it means that the LVDS channel isn't
  207. * stable yet.
  208. */
  209. printf("Display didn't stabilize.\n");
  210. printf("This may be because the LVDS port is still in powersave mode.\n");
  211. mdelay(50);
  212. }
  213. return -EINVAL;
  214. }
  215. static void enable_hdmi(struct display_info_t const *dev)
  216. {
  217. imx_enable_hdmi_phy();
  218. }
  219. static int lvds_enabled;
  220. static void enable_lvds(struct display_info_t const *dev)
  221. {
  222. if (lvds_enabled)
  223. return;
  224. /* ITE IT6251 power enable. */
  225. gpio_request(NOVENA_ITE6251_PWR_GPIO, "ite6251-power");
  226. gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
  227. mdelay(10);
  228. gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
  229. mdelay(20);
  230. lvds_enabled = 1;
  231. }
  232. static int detect_lvds(struct display_info_t const *dev)
  233. {
  234. int ret, loops = 250;
  235. enable_lvds(dev);
  236. ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
  237. if (ret) {
  238. puts("Cannot select IT6251 I2C bus.\n");
  239. return 0;
  240. }
  241. /* Wait up-to ~250 mS for the LVDS to come up. */
  242. while (--loops) {
  243. ret = it6251_ready();
  244. if (ret)
  245. return ret;
  246. mdelay(1);
  247. }
  248. return 0;
  249. }
  250. struct display_info_t const displays[] = {
  251. {
  252. /* HDMI Output */
  253. .bus = -1,
  254. .addr = 0,
  255. .pixfmt = IPU_PIX_FMT_RGB24,
  256. .detect = detect_hdmi,
  257. .enable = enable_hdmi,
  258. .mode = {
  259. .name = "HDMI",
  260. .refresh = 60,
  261. .xres = 1024,
  262. .yres = 768,
  263. .pixclock = 15384,
  264. .left_margin = 220,
  265. .right_margin = 40,
  266. .upper_margin = 21,
  267. .lower_margin = 7,
  268. .hsync_len = 60,
  269. .vsync_len = 10,
  270. .sync = FB_SYNC_EXT,
  271. .vmode = FB_VMODE_NONINTERLACED
  272. },
  273. }, {
  274. /* LVDS Output: N133HSE-EA1 Rev. C1 */
  275. .bus = -1,
  276. .pixfmt = IPU_PIX_FMT_RGB24,
  277. .detect = detect_lvds,
  278. .enable = enable_lvds,
  279. .mode = {
  280. .name = "Chimei-FHD",
  281. .refresh = 60,
  282. .xres = 1920,
  283. .yres = 1080,
  284. .pixclock = 15384,
  285. .left_margin = 148,
  286. .right_margin = 88,
  287. .upper_margin = 36,
  288. .lower_margin = 4,
  289. .hsync_len = 44,
  290. .vsync_len = 5,
  291. .sync = FB_SYNC_HOR_HIGH_ACT |
  292. FB_SYNC_VERT_HIGH_ACT |
  293. FB_SYNC_EXT,
  294. .vmode = FB_VMODE_NONINTERLACED,
  295. },
  296. },
  297. };
  298. size_t display_count = ARRAY_SIZE(displays);
  299. static void enable_vpll(void)
  300. {
  301. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  302. int timeout = 100000;
  303. setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
  304. clrsetbits_le32(&ccm->analog_pll_video,
  305. BM_ANADIG_PLL_VIDEO_DIV_SELECT |
  306. BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
  307. BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
  308. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
  309. writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
  310. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
  311. clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
  312. while (timeout--)
  313. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  314. break;
  315. if (timeout < 0)
  316. printf("Warning: video pll lock timeout!\n");
  317. clrsetbits_le32(&ccm->analog_pll_video,
  318. BM_ANADIG_PLL_VIDEO_BYPASS,
  319. BM_ANADIG_PLL_VIDEO_ENABLE);
  320. }
  321. void setup_display_clock(void)
  322. {
  323. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  324. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  325. enable_ipu_clock();
  326. enable_vpll();
  327. imx_setup_hdmi();
  328. /* Turn on IPU LDB DI0 clocks */
  329. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  330. /* Switch LDB DI0 to PLL5 (Video PLL) */
  331. clrsetbits_le32(&mxc_ccm->cs2cdr,
  332. MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
  333. (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  334. /* LDB clock div by 3.5 */
  335. clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  336. /* DI0 clock derived from ldb_di0_clk */
  337. clrsetbits_le32(&mxc_ccm->chsccdr,
  338. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
  339. (CHSCCDR_CLK_SEL_LDB_DI0 <<
  340. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
  341. );
  342. /* Enable both LVDS channels, both connected to DI0. */
  343. writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
  344. IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
  345. IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
  346. IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
  347. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
  348. IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
  349. IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
  350. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
  351. &iomux->gpr[2]);
  352. clrsetbits_le32(&iomux->gpr[3],
  353. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  354. IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
  355. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  356. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
  357. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  358. IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
  359. );
  360. }
  361. void setup_display_lvds(void)
  362. {
  363. int ret;
  364. ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
  365. if (ret) {
  366. puts("Cannot select LVDS-to-eDP I2C bus.\n");
  367. return;
  368. }
  369. /* The IT6251 should be ready now, if it's not, it's not connected. */
  370. ret = it6251_ready();
  371. if (!ret)
  372. return;
  373. /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
  374. ret = it6251_init();
  375. if (!ret) {
  376. gpio_request(NOVENA_BACKLIGHT_PWR_GPIO, "backlight-power");
  377. gpio_request(NOVENA_BACKLIGHT_PWM_GPIO, "backlight-pwm");
  378. /* Backlight power enable. */
  379. gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
  380. /* PWM backlight pin, always on for full brightness. */
  381. gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
  382. }
  383. }