novena_spl.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Novena SPL
  4. *
  5. * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  6. */
  7. #include <common.h>
  8. #include <clock_legacy.h>
  9. #include <init.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/iomux.h>
  13. #include <asm/arch/mx6-ddr.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <asm/mach-imx/iomux-v3.h>
  19. #include <asm/mach-imx/mxc_i2c.h>
  20. #include <asm/arch/crm_regs.h>
  21. #include <i2c.h>
  22. #include <mmc.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <spl.h>
  25. #include <linux/delay.h>
  26. #include <asm/arch/mx6-ddr.h>
  27. #include "novena.h"
  28. #define UART_PAD_CTRL \
  29. (PAD_CTL_PKE | PAD_CTL_PUE | \
  30. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  31. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  32. #define USDHC_PAD_CTRL \
  33. (PAD_CTL_PKE | PAD_CTL_PUE | \
  34. PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  35. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  36. #define ENET_PAD_CTRL \
  37. (PAD_CTL_PKE | PAD_CTL_PUE | \
  38. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  39. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  40. #define ENET_PHY_CFG_PAD_CTRL \
  41. (PAD_CTL_PKE | PAD_CTL_PUE | \
  42. PAD_CTL_PUS_22K_UP | PAD_CTL_HYS)
  43. #define RGMII_PAD_CTRL \
  44. (PAD_CTL_PKE | PAD_CTL_PUE | \
  45. PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  46. #define SPI_PAD_CTRL \
  47. (PAD_CTL_HYS | \
  48. PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
  49. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  50. #define I2C_PAD_CTRL \
  51. (PAD_CTL_PKE | PAD_CTL_PUE | \
  52. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  53. PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \
  54. PAD_CTL_ODE)
  55. #define BUTTON_PAD_CTRL \
  56. (PAD_CTL_PKE | PAD_CTL_PUE | \
  57. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  58. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  59. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  60. /*
  61. * Audio
  62. */
  63. static iomux_v3_cfg_t audio_pads[] = {
  64. /* AUD_PWRON */
  65. MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
  66. };
  67. static void novena_spl_setup_iomux_audio(void)
  68. {
  69. imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads));
  70. gpio_direction_output(NOVENA_AUDIO_PWRON, 1);
  71. }
  72. /*
  73. * ENET
  74. */
  75. static iomux_v3_cfg_t enet_pads1[] = {
  76. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  79. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  80. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  81. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  82. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  83. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  84. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85. /* pin 35, PHY_AD2 */
  86. MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  87. /* pin 32, MODE0 */
  88. MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  89. /* pin 31, MODE1 */
  90. MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  91. /* pin 28, MODE2 */
  92. MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  93. /* pin 27, MODE3 */
  94. MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  95. /* pin 33, CLK125_EN */
  96. MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  97. /* pin 42 PHY nRST */
  98. MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  99. };
  100. static iomux_v3_cfg_t enet_pads2[] = {
  101. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  102. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  103. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  104. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  105. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  106. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  107. };
  108. static void novena_spl_setup_iomux_enet(void)
  109. {
  110. imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  111. /* Assert Ethernet PHY nRST */
  112. gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
  113. /*
  114. * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
  115. * de-assertion. The intention is to use weak signal drivers (pull-ups)
  116. * to prevent the conflict between PHY pins becoming outputs after
  117. * reset and imx6 still driving the pins. The issue is described in PHY
  118. * datasheet, p.14
  119. */
  120. gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
  121. gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
  122. gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
  123. gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
  124. gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
  125. gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
  126. /* Following reset timing (p.53, fig.8 from the PHY datasheet) */
  127. mdelay(10);
  128. /* De-assert Ethernet PHY nRST */
  129. gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  130. /* PHY is now configured, connect FEC to the pads */
  131. imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  132. /*
  133. * PHY datasheet recommends on p.53 to wait at least 100us after reset
  134. * before using MII, so we enforce the delay here
  135. */
  136. udelay(100);
  137. }
  138. /*
  139. * FPGA
  140. */
  141. static iomux_v3_cfg_t fpga_pads[] = {
  142. /* FPGA_RESET_N */
  143. MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  144. };
  145. static void novena_spl_setup_iomux_fpga(void)
  146. {
  147. imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads));
  148. gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0);
  149. }
  150. /*
  151. * GPIO Button
  152. */
  153. static iomux_v3_cfg_t button_pads[] = {
  154. /* Debug */
  155. MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  156. };
  157. static void novena_spl_setup_iomux_buttons(void)
  158. {
  159. imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads));
  160. }
  161. /*
  162. * I2C
  163. */
  164. /*
  165. * I2C1:
  166. * 0x1d ... MMA7455L
  167. * 0x30 ... SO-DIMM temp sensor
  168. * 0x44 ... STMPE610
  169. * 0x50 ... SO-DIMM ID
  170. */
  171. struct i2c_pads_info i2c_pad_info0 = {
  172. .scl = {
  173. .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  174. .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  175. .gp = IMX_GPIO_NR(3, 21)
  176. },
  177. .sda = {
  178. .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  179. .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  180. .gp = IMX_GPIO_NR(3, 28)
  181. }
  182. };
  183. /*
  184. * I2C2:
  185. * 0x08 ... PMIC
  186. * 0x3a ... HDMI DCC
  187. * 0x50 ... HDMI DCC
  188. */
  189. static struct i2c_pads_info i2c_pad_info1 = {
  190. .scl = {
  191. .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  192. .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  193. .gp = IMX_GPIO_NR(2, 30)
  194. },
  195. .sda = {
  196. .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
  197. .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
  198. .gp = IMX_GPIO_NR(3, 16)
  199. }
  200. };
  201. /*
  202. * I2C3:
  203. * 0x11 ... ES8283
  204. * 0x50 ... LCD EDID
  205. * 0x56 ... EEPROM
  206. */
  207. static struct i2c_pads_info i2c_pad_info2 = {
  208. .scl = {
  209. .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
  210. .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
  211. .gp = IMX_GPIO_NR(3, 17)
  212. },
  213. .sda = {
  214. .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
  215. .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
  216. .gp = IMX_GPIO_NR(3, 18)
  217. }
  218. };
  219. static void novena_spl_setup_iomux_i2c(void)
  220. {
  221. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  222. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  223. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  224. }
  225. /*
  226. * PCI express
  227. */
  228. #ifdef CONFIG_CMD_PCI
  229. static iomux_v3_cfg_t pcie_pads[] = {
  230. /* "Reset" pin */
  231. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  232. /* "Power on" pin */
  233. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  234. /* "Wake up" pin (input) */
  235. MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  236. /* "Disable endpoint" (rfkill) pin */
  237. MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  238. };
  239. static void novena_spl_setup_iomux_pcie(void)
  240. {
  241. imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  242. /* Ensure PCIe is powered down */
  243. gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0);
  244. /* Put the card into reset */
  245. gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0);
  246. /* Input signal to wake system from mPCIe card */
  247. gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO);
  248. /* Drive RFKILL high, to ensure the radio is turned on */
  249. gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1);
  250. }
  251. #else
  252. static inline void novena_spl_setup_iomux_pcie(void) {}
  253. #endif
  254. /*
  255. * SDHC
  256. */
  257. static iomux_v3_cfg_t usdhc2_pads[] = {
  258. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  259. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  260. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  261. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  262. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  263. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  264. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
  265. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  266. };
  267. static iomux_v3_cfg_t usdhc3_pads[] = {
  268. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  269. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  270. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  271. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  272. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  273. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  274. };
  275. static void novena_spl_setup_iomux_sdhc(void)
  276. {
  277. imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  278. imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  279. /* Big SD write-protect and card-detect */
  280. gpio_direction_input(IMX_GPIO_NR(1, 2));
  281. gpio_direction_input(IMX_GPIO_NR(1, 4));
  282. }
  283. /*
  284. * SPI
  285. */
  286. #ifdef CONFIG_MXC_SPI
  287. static iomux_v3_cfg_t ecspi3_pads[] = {
  288. /* SS1 */
  289. MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  290. MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  291. MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  292. MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  293. MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  294. MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  295. MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL),
  296. };
  297. static void novena_spl_setup_iomux_spi(void)
  298. {
  299. imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
  300. /* De-assert the nCS */
  301. gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1);
  302. gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1);
  303. gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1);
  304. }
  305. #else
  306. static void novena_spl_setup_iomux_spi(void) {}
  307. #endif
  308. /*
  309. * UART
  310. */
  311. static iomux_v3_cfg_t const uart2_pads[] = {
  312. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  313. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  314. };
  315. static iomux_v3_cfg_t const uart3_pads[] = {
  316. MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  317. MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  318. };
  319. static iomux_v3_cfg_t const uart4_pads[] = {
  320. MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  321. MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  322. MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  323. MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  324. };
  325. static void novena_spl_setup_iomux_uart(void)
  326. {
  327. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  328. imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  329. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  330. }
  331. /*
  332. * Video
  333. */
  334. #ifdef CONFIG_VIDEO
  335. static iomux_v3_cfg_t hdmi_pads[] = {
  336. /* "Ghost HPD" pin */
  337. MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  338. /* LCD_PWR_CTL */
  339. MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  340. /* LCD_BL_ON */
  341. MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  342. /* GPIO_PWM1 */
  343. MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  344. };
  345. static void novena_spl_setup_iomux_video(void)
  346. {
  347. imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
  348. gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
  349. }
  350. #else
  351. static inline void novena_spl_setup_iomux_video(void) {}
  352. #endif
  353. /*
  354. * SPL boots from uSDHC card
  355. */
  356. #ifdef CONFIG_FSL_ESDHC_IMX
  357. static struct fsl_esdhc_cfg usdhc_cfg = {
  358. USDHC3_BASE_ADDR, 0, 4
  359. };
  360. int board_mmc_getcd(struct mmc *mmc)
  361. {
  362. /* There is no CD for a microSD card, assume always present. */
  363. return 1;
  364. }
  365. int board_mmc_init(struct bd_info *bis)
  366. {
  367. usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  368. return fsl_esdhc_initialize(bis, &usdhc_cfg);
  369. }
  370. #endif
  371. /* Configure MX6Q/DUAL mmdc DDR io registers */
  372. static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
  373. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  374. .dram_sdclk_0 = 0x00020038,
  375. .dram_sdclk_1 = 0x00020038,
  376. .dram_cas = 0x00000038,
  377. .dram_ras = 0x00000038,
  378. .dram_reset = 0x00000038,
  379. /* SDCKE[0:1]: 100k pull-up */
  380. .dram_sdcke0 = 0x00000038,
  381. .dram_sdcke1 = 0x00000038,
  382. /* SDBA2: pull-up disabled */
  383. .dram_sdba2 = 0x00000000,
  384. /* SDODT[0:1]: 100k pull-up, 40 ohm */
  385. .dram_sdodt0 = 0x00000038,
  386. .dram_sdodt1 = 0x00000038,
  387. /* SDQS[0:7]: Differential input, 40 ohm */
  388. .dram_sdqs0 = 0x00000038,
  389. .dram_sdqs1 = 0x00000038,
  390. .dram_sdqs2 = 0x00000038,
  391. .dram_sdqs3 = 0x00000038,
  392. .dram_sdqs4 = 0x00000038,
  393. .dram_sdqs5 = 0x00000038,
  394. .dram_sdqs6 = 0x00000038,
  395. .dram_sdqs7 = 0x00000038,
  396. /* DQM[0:7]: Differential input, 40 ohm */
  397. .dram_dqm0 = 0x00000038,
  398. .dram_dqm1 = 0x00000038,
  399. .dram_dqm2 = 0x00000038,
  400. .dram_dqm3 = 0x00000038,
  401. .dram_dqm4 = 0x00000038,
  402. .dram_dqm5 = 0x00000038,
  403. .dram_dqm6 = 0x00000038,
  404. .dram_dqm7 = 0x00000038,
  405. };
  406. /* Configure MX6Q/DUAL mmdc GRP io registers */
  407. static struct mx6dq_iomux_grp_regs novena_grp_ioregs = {
  408. /* DDR3 */
  409. .grp_ddr_type = 0x000c0000,
  410. .grp_ddrmode_ctl = 0x00020000,
  411. /* Disable DDR pullups */
  412. .grp_ddrpke = 0x00000000,
  413. /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  414. .grp_addds = 0x00000038,
  415. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  416. .grp_ctlds = 0x00000038,
  417. /* DATA[00:63]: Differential input, 40 ohm */
  418. .grp_ddrmode = 0x00020000,
  419. .grp_b0ds = 0x00000038,
  420. .grp_b1ds = 0x00000038,
  421. .grp_b2ds = 0x00000038,
  422. .grp_b3ds = 0x00000038,
  423. .grp_b4ds = 0x00000038,
  424. .grp_b5ds = 0x00000038,
  425. .grp_b6ds = 0x00000038,
  426. .grp_b7ds = 0x00000038,
  427. };
  428. static struct mx6_mmdc_calibration novena_mmdc_calib = {
  429. /* write leveling calibration determine */
  430. .p0_mpwldectrl0 = 0x00420048,
  431. .p0_mpwldectrl1 = 0x006f0059,
  432. .p1_mpwldectrl0 = 0x005a0104,
  433. .p1_mpwldectrl1 = 0x01070113,
  434. /* Read DQS Gating calibration */
  435. .p0_mpdgctrl0 = 0x437c040b,
  436. .p0_mpdgctrl1 = 0x0413040e,
  437. .p1_mpdgctrl0 = 0x444f0446,
  438. .p1_mpdgctrl1 = 0x044d0422,
  439. /* Read Calibration: DQS delay relative to DQ read access */
  440. .p0_mprddlctl = 0x4c424249,
  441. .p1_mprddlctl = 0x4e48414f,
  442. /* Write Calibration: DQ/DM delay relative to DQS write access */
  443. .p0_mpwrdlctl = 0x42414641,
  444. .p1_mpwrdlctl = 0x46374b43,
  445. };
  446. static struct mx6_ddr_sysinfo novena_ddr_info = {
  447. /* Width of data bus: 0=16, 1=32, 2=64 */
  448. .dsize = 2,
  449. /* Config for full 4GB range so that get_mem_size() works */
  450. .cs_density = 32, /* 32Gb per CS */
  451. /* Single chip select */
  452. .ncs = 1,
  453. .cs1_mirror = 0,
  454. .rtt_wr = 0, /* RTT_Wr = RZQ/4 */
  455. .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
  456. .walat = 0, /* Write additional latency */
  457. .ralat = 5, /* Read additional latency */
  458. .mif3_mode = 3, /* Command prediction working mode */
  459. .bi_on = 1, /* Bank interleaving enabled */
  460. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  461. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  462. .refsel = 1, /* Refresh cycles at 32KHz */
  463. .refr = 7, /* 8 refresh commands per refresh cycle */
  464. };
  465. static struct mx6_ddr3_cfg elpida_4gib_1600 = {
  466. .mem_speed = 1600,
  467. .density = 4,
  468. .width = 64,
  469. .banks = 8,
  470. .rowaddr = 16,
  471. .coladdr = 10,
  472. .pagesz = 2,
  473. .trcd = 1375,
  474. .trcmin = 4875,
  475. .trasmin = 3500,
  476. };
  477. static void ccgr_init(void)
  478. {
  479. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  480. writel(0x00C03F3F, &ccm->CCGR0);
  481. writel(0x0030FC03, &ccm->CCGR1);
  482. writel(0x0FFFC000, &ccm->CCGR2);
  483. writel(0x3FF00000, &ccm->CCGR3);
  484. writel(0xFFFFF300, &ccm->CCGR4);
  485. writel(0x0F0000C3, &ccm->CCGR5);
  486. writel(0x000003FF, &ccm->CCGR6);
  487. }
  488. /*
  489. * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  490. * - we have a stack and a place to store GD, both in SRAM
  491. * - no variable global data is available
  492. */
  493. void board_init_f(ulong dummy)
  494. {
  495. /* setup AIPS and disable watchdog */
  496. arch_cpu_init();
  497. ccgr_init();
  498. gpr_init();
  499. /* setup GP timer */
  500. timer_init();
  501. #ifdef CONFIG_BOARD_POSTCLK_INIT
  502. board_postclk_init();
  503. #endif
  504. #ifdef CONFIG_FSL_ESDHC_IMX
  505. get_clocks();
  506. #endif
  507. /* Setup IOMUX and configure basics. */
  508. novena_spl_setup_iomux_audio();
  509. novena_spl_setup_iomux_buttons();
  510. novena_spl_setup_iomux_enet();
  511. novena_spl_setup_iomux_fpga();
  512. novena_spl_setup_iomux_i2c();
  513. novena_spl_setup_iomux_pcie();
  514. novena_spl_setup_iomux_sdhc();
  515. novena_spl_setup_iomux_spi();
  516. novena_spl_setup_iomux_uart();
  517. novena_spl_setup_iomux_video();
  518. /* UART clocks enabled and gd valid - init serial console */
  519. preloader_console_init();
  520. /* Start the DDR DRAM */
  521. mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
  522. mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
  523. /* Perform DDR DRAM calibration */
  524. udelay(100);
  525. mmdc_do_write_level_calibration(&novena_ddr_info);
  526. mmdc_do_dqs_calibration(&novena_ddr_info);
  527. }