kwbimage-memphis.cfg 5.9 KB

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  1. # SPDX-License-Identifier: GPL-2.0+
  2. #
  3. # (C) Copyright 2010
  4. # Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. #
  6. # (C) Copyright 2011
  7. # Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
  8. # Refer doc/README.kwbimage for more details about how-to configure
  9. # and create kirkwood boot image
  10. #
  11. # Boot Media configurations
  12. BOOT_FROM spi # Boot from SPI flash
  13. DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
  14. # bit 3-0: MPPSel0 2, NF_IO[2]
  15. # bit 7-4: MPPSel1 2, NF_IO[3]
  16. # bit 12-8: MPPSel2 2, NF_IO[4]
  17. # bit 15-12: MPPSel3 2, NF_IO[5]
  18. # bit 19-16: MPPSel4 1, NF_IO[6]
  19. # bit 23-20: MPPSel5 1, NF_IO[7]
  20. # bit 27-24: MPPSel6 1, SYSRST_O
  21. # bit 31-28: MPPSel7 0, GPO[7]
  22. DATA 0xFFD10004 0x03303300
  23. DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
  24. # bit 3-0: MPPSel16 0, GPIO[16]
  25. # bit 7-4: MPPSel17 0, GPIO[17]
  26. # bit 12-8: MPPSel18 1, NF_IO[0]
  27. # bit 15-12: MPPSel19 1, NF_IO[1]
  28. # bit 19-16: MPPSel20 0, GPIO[20]
  29. # bit 23-20: MPPSel21 0, GPIO[21]
  30. # bit 27-24: MPPSel22 0, GPIO[22]
  31. # bit 31-28: MPPSel23 0, GPIO[23]
  32. DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
  33. DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
  34. DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
  35. # NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
  36. # If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
  37. #Dram initalization
  38. DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
  39. # bit13-0: 0x4E0 (DDR2 clks refresh rate)
  40. # bit23-14: zero
  41. # bit24: 1= enable exit self refresh mode on DDR access
  42. # bit25: 1 required
  43. # bit29-26: zero
  44. # bit31-30: 01
  45. DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
  46. # bit 3-0: 0 reserved
  47. # bit 4: 0=addr/cmd in smame cycle
  48. # bit 5: 0=clk is driven during self refresh, we don't care for APX
  49. # bit 6: 0=use recommended falling edge of clk for addr/cmd
  50. # bit14: 0=input buffer always powered up
  51. # bit18: 1=cpu lock transaction enabled
  52. # bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
  53. # bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
  54. # bit30-28: 3 required
  55. # bit31: 0=no additional STARTBURST delay
  56. DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
  57. # bit3-0: TRAS lsbs
  58. # bit7-4: TRCD
  59. # bit11- 8: TRP
  60. # bit15-12: TWR
  61. # bit19-16: TWTR
  62. # bit20: TRAS msb
  63. # bit23-21: 0x0
  64. # bit27-24: TRRD
  65. # bit31-28: TRTP
  66. DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
  67. # bit6-0: TRFC
  68. # bit8-7: TR2R
  69. # bit10-9: TR2W
  70. # bit12-11: TW2W
  71. # bit31-13: zero required
  72. DATA 0xFFD01410 0x00000001 # DDR Address Control
  73. # bit1-0: 01, Cs0width=x16
  74. # bit3-2: 00, Cs0size=2Gb
  75. # bit5-4: 00, Cs2width=nonexistent
  76. # bit7-6: 00, Cs1size =nonexistent
  77. # bit9-8: 00, Cs2width=nonexistent
  78. # bit11-10: 00, Cs2size =nonexistent
  79. # bit13-12: 00, Cs3width=nonexistent
  80. # bit15-14: 00, Cs3size =nonexistent
  81. # bit16: 0, Cs0AddrSel
  82. # bit17: 0, Cs1AddrSel
  83. # bit18: 0, Cs2AddrSel
  84. # bit19: 0, Cs3AddrSel
  85. # bit31-20: 0 required
  86. DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
  87. # bit0: 0, OpenPage enabled
  88. # bit31-1: 0 required
  89. DATA 0xFFD01418 0x00000000 # DDR Operation
  90. # bit3-0: 0x0, DDR cmd
  91. # bit31-4: 0 required
  92. DATA 0xFFD0141C 0x00000652 # DDR Mode
  93. DATA 0xFFD01420 0x00000006 # DDR Extended Mode
  94. # bit0: 0, DDR DLL enabled
  95. # bit1: 1, DDR drive strenght reduced
  96. # bit2: 1, DDR ODT control lsd disabled
  97. # bit5-3: 000, required
  98. # bit6: 0, DDR ODT control msb disabled
  99. # bit9-7: 000, required
  100. # bit10: 0, differential DQS enabled
  101. # bit11: 0, required
  102. # bit12: 0, DDR output buffer enabled
  103. # bit31-13: 0 required
  104. DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
  105. # bit2-0: 111, required
  106. # bit3 : 1 , MBUS Burst Chop disabled
  107. # bit6-4: 111, required
  108. # bit7 : 0
  109. # bit8 : 1 , add a sample stage
  110. # bit9 : 0 , no half clock cycle addition to dataout
  111. # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
  112. # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
  113. # bit15-12: 1111 required
  114. # bit31-16: 0 required
  115. DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
  116. # bit3-0 : 0000, required
  117. # bit7-4 : 0010, M_ODT assertion 2 cycles after read
  118. # bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
  119. # bit15-12: 0100, internal ODT assertion 4 cycles after read
  120. # bit19-16: 1000, internal ODT de-assertion 8 cycles after read
  121. # bit31-20: 0 , required
  122. DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High
  123. # bit3-0 : 0001, M_ODT assertion same cycle as write
  124. # bit7-4 : 0101, M_ODT de-assertion x cycles after write
  125. # bit11-8 : 0100, internal ODT assertion x cycles after write
  126. # bit15-12: 1000, internal ODT de-assertion x cycles after write
  127. DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
  128. DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
  129. # bit0: 1, Window enabled
  130. # bit1: 0, Write Protect disabled
  131. # bit3-2: 00, CS0 hit selected
  132. # bit23-4: ones, required
  133. # bit31-24: 0x0F, Size (i.e. 256MB)
  134. DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
  135. DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
  136. DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
  137. DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
  138. # bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
  139. # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
  140. DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
  141. # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
  142. # bit3-2: 00, ODT1 controlled by register
  143. # bit31-4: zero, required
  144. DATA 0xFFD0149C 0x0000F801 # CPU ODT Control
  145. # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
  146. # bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
  147. # bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
  148. # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
  149. # bit13-12:3, STARTBURST ODT buffer selected, 50 ohm
  150. # bit14 :1, STARTBURST ODT enabled
  151. # bit15 :1, Use ODT Block
  152. DATA 0xFFD01480 0x00000001 # DDR Initialization Control
  153. # bit0=1, enable DDR init upon this register write
  154. # End of Header extension
  155. DATA 0x0 0x0