kp_imx6q_tpc_spl.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * K+P iMX6Q KP_IMX6Q_TPC board configuration
  4. *
  5. * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/crm_regs.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/mx6-ddr.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/io.h>
  16. #include <errno.h>
  17. #include <spl.h>
  18. #include <linux/delay.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static void ccgr_init(void)
  21. {
  22. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  23. writel(0x00C03F3F, &ccm->CCGR0);
  24. writel(0x0030FC03, &ccm->CCGR1);
  25. writel(0x0FFFC000, &ccm->CCGR2);
  26. writel(0x3FF00000, &ccm->CCGR3);
  27. writel(0x00FFF300, &ccm->CCGR4);
  28. writel(0x0F0000C3, &ccm->CCGR5);
  29. writel(0x000003FF, &ccm->CCGR6);
  30. }
  31. /* DDR3 */
  32. static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  33. .dram_sdclk_0 = 0x00000030,
  34. .dram_sdclk_1 = 0x00000030,
  35. .dram_cas = 0x00000030,
  36. .dram_ras = 0x00000030,
  37. .dram_reset = 0x00000030,
  38. .dram_sdcke0 = 0x00003000,
  39. .dram_sdcke1 = 0x00003000,
  40. .dram_sdba2 = 0x00000000,
  41. .dram_sdodt0 = 0x00000030,
  42. .dram_sdodt1 = 0x00000030,
  43. .dram_sdqs0 = 0x00000018,
  44. .dram_sdqs1 = 0x00000018,
  45. .dram_sdqs2 = 0x00000018,
  46. .dram_sdqs3 = 0x00000018,
  47. .dram_sdqs4 = 0x00000018,
  48. .dram_sdqs5 = 0x00000018,
  49. .dram_sdqs6 = 0x00000018,
  50. .dram_sdqs7 = 0x00000018,
  51. .dram_dqm0 = 0x00000018,
  52. .dram_dqm1 = 0x00000018,
  53. .dram_dqm2 = 0x00000018,
  54. .dram_dqm3 = 0x00000018,
  55. .dram_dqm4 = 0x00000018,
  56. .dram_dqm5 = 0x00000018,
  57. .dram_dqm6 = 0x00000018,
  58. .dram_dqm7 = 0x00000018,
  59. };
  60. static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  61. .grp_ddr_type = 0x000c0000,
  62. .grp_ddrmode_ctl = 0x00020000,
  63. .grp_ddrpke = 0x00000000,
  64. .grp_addds = 0x00000030,
  65. .grp_ctlds = 0x00000030,
  66. .grp_ddrmode = 0x00020000,
  67. .grp_b0ds = 0x00000018,
  68. .grp_b1ds = 0x00000018,
  69. .grp_b2ds = 0x00000018,
  70. .grp_b3ds = 0x00000018,
  71. .grp_b4ds = 0x00000018,
  72. .grp_b5ds = 0x00000018,
  73. .grp_b6ds = 0x00000018,
  74. .grp_b7ds = 0x00000018,
  75. };
  76. static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  77. .p0_mpwldectrl0 = 0x001F001F,
  78. .p0_mpwldectrl1 = 0x001F001F,
  79. .p1_mpwldectrl0 = 0x001F001F,
  80. .p1_mpwldectrl1 = 0x001F001F,
  81. .p0_mpdgctrl0 = 0x43270338,
  82. .p0_mpdgctrl1 = 0x03200314,
  83. .p1_mpdgctrl0 = 0x431A032F,
  84. .p1_mpdgctrl1 = 0x03200263,
  85. .p0_mprddlctl = 0x4B434748,
  86. .p1_mprddlctl = 0x4445404C,
  87. .p0_mpwrdlctl = 0x38444542,
  88. .p1_mpwrdlctl = 0x4935493A,
  89. };
  90. /* MT41K256M16 (4Gb density) */
  91. static const struct mx6_ddr3_cfg mt41k256m16 = {
  92. .mem_speed = 1600,
  93. .density = 4,
  94. .width = 16,
  95. .banks = 8,
  96. .rowaddr = 15,
  97. .coladdr = 10,
  98. .pagesz = 2,
  99. .trcd = 1375,
  100. .trcmin = 4875,
  101. .trasmin = 3500,
  102. };
  103. #ifdef CONFIG_MX6_DDRCAL
  104. static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
  105. {
  106. struct mx6_mmdc_calibration calibration = {0};
  107. mmdc_read_calibration(sysinfo, &calibration);
  108. debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
  109. debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
  110. debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
  111. debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
  112. debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
  113. debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
  114. debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
  115. debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
  116. debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
  117. debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
  118. debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
  119. debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
  120. }
  121. static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
  122. {
  123. int ret;
  124. /* Perform DDR DRAM calibration */
  125. udelay(100);
  126. ret = mmdc_do_write_level_calibration(sysinfo);
  127. if (ret) {
  128. printf("DDR: Write level calibration error [%d]\n", ret);
  129. return;
  130. }
  131. ret = mmdc_do_dqs_calibration(sysinfo);
  132. if (ret) {
  133. printf("DDR: DQS calibration error [%d]\n", ret);
  134. return;
  135. }
  136. spl_dram_print_cal(sysinfo);
  137. }
  138. #endif /* CONFIG_MX6_DDRCAL */
  139. static void spl_dram_init(void)
  140. {
  141. struct mx6_ddr_sysinfo sysinfo = {
  142. /* width of data bus:0=16,1=32,2=64 */
  143. .dsize = 2,
  144. /* config for full 4GB range so that get_mem_size() works */
  145. .cs_density = 32, /* 32Gb per CS */
  146. /* single chip select */
  147. .ncs = 1,
  148. .cs1_mirror = 0,
  149. .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  150. .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
  151. .walat = 1, /* Write additional latency */
  152. .ralat = 5, /* Read additional latency */
  153. .mif3_mode = 3, /* Command prediction working mode */
  154. .bi_on = 1, /* Bank interleaving enabled */
  155. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  156. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  157. .pd_fast_exit = 1, /* enable precharge power-down fast exit */
  158. .ddr_type = DDR_TYPE_DDR3,
  159. .refsel = 1, /* Refresh cycles at 32KHz */
  160. .refr = 7, /* 8 refresh commands per refresh cycle */
  161. };
  162. mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  163. mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
  164. #ifdef CONFIG_MX6_DDRCAL
  165. spl_dram_perform_cal(&sysinfo);
  166. #endif
  167. }
  168. void board_boot_order(u32 *spl_boot_list)
  169. {
  170. u32 boot_device = spl_boot_device();
  171. u32 reg = imx6_src_get_boot_mode();
  172. reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
  173. debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg);
  174. if (boot_device == BOOT_DEVICE_MMC1)
  175. if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC)
  176. boot_device = BOOT_DEVICE_MMC2;
  177. spl_boot_list[0] = boot_device;
  178. /*
  179. * Below boot device is a 'fallback' - it shall always be possible to
  180. * boot from SD card
  181. */
  182. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  183. }
  184. void board_init_f(ulong dummy)
  185. {
  186. /* setup AIPS and disable watchdog */
  187. arch_cpu_init();
  188. ccgr_init();
  189. gpr_init();
  190. /* setup GP timer */
  191. timer_init();
  192. /* Early - pre reloc - driver model setup */
  193. spl_early_init();
  194. /* UART clocks enabled and gd valid - init serial console */
  195. preloader_console_init();
  196. /* DDR initialization */
  197. spl_dram_init();
  198. /* Clear the BSS. */
  199. memset(__bss_start, 0, __bss_end - __bss_start);
  200. }