board.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
  4. *
  5. * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
  6. */
  7. #include <common.h>
  8. #include <env.h>
  9. #include <errno.h>
  10. #include <init.h>
  11. #include <malloc.h>
  12. #include <net.h>
  13. #include <serial.h>
  14. #include <spl.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/omap.h>
  18. #include <asm/arch/ddr_defs.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/mmc_host_def.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/io.h>
  24. #include <asm/emif.h>
  25. #include <asm/gpio.h>
  26. #include <i2c.h>
  27. #include <miiphy.h>
  28. #include <cpsw.h>
  29. #include <fdt_support.h>
  30. #include <mtd_node.h>
  31. #include <jffs2/load_kernel.h>
  32. #include "board.h"
  33. DECLARE_GLOBAL_DATA_PTR;
  34. /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
  35. * and control IGEP0034 green and red LEDs.
  36. * U-boot configures these pins as input pullup to detect board revision:
  37. * IGEP0034-LITE = 0b00
  38. * IGEP0034 (FULL) = 0b01
  39. * IGEP0033 = 0b1X
  40. */
  41. #define GPIO_GREEN_REVISION 27
  42. #define GPIO_RED_REVISION 26
  43. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  44. /*
  45. * Routine: get_board_revision
  46. * Description: Returns the board revision
  47. */
  48. static int get_board_revision(void)
  49. {
  50. int revision;
  51. gpio_request(GPIO_GREEN_REVISION, "green_revision");
  52. gpio_direction_input(GPIO_GREEN_REVISION);
  53. revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
  54. gpio_free(GPIO_GREEN_REVISION);
  55. gpio_request(GPIO_RED_REVISION, "red_revision");
  56. gpio_direction_input(GPIO_RED_REVISION);
  57. revision = revision + gpio_get_value(GPIO_RED_REVISION);
  58. gpio_free(GPIO_RED_REVISION);
  59. return revision;
  60. }
  61. #ifdef CONFIG_SPL_BUILD
  62. /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
  63. static const struct ddr_data ddr3_igep0034_data = {
  64. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  65. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  66. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  67. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  68. };
  69. static const struct ddr_data ddr3_igep0034_lite_data = {
  70. .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  71. .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  72. .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  73. .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  74. };
  75. static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
  76. .cmd0csratio = MT41K256M16HA125E_RATIO,
  77. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  78. .cmd1csratio = MT41K256M16HA125E_RATIO,
  79. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  80. .cmd2csratio = MT41K256M16HA125E_RATIO,
  81. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  82. };
  83. static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
  84. .cmd0csratio = K4B2G1646EBIH9_RATIO,
  85. .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  86. .cmd1csratio = K4B2G1646EBIH9_RATIO,
  87. .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  88. .cmd2csratio = K4B2G1646EBIH9_RATIO,
  89. .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  90. };
  91. static struct emif_regs ddr3_igep0034_emif_reg_data = {
  92. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  93. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  94. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  95. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  96. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  97. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  98. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  99. };
  100. static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
  101. .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
  102. .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
  103. .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
  104. .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
  105. .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
  106. .zq_config = K4B2G1646EBIH9_ZQ_CFG,
  107. .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
  108. };
  109. const struct ctrl_ioregs ioregs_igep0034 = {
  110. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  111. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  112. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  113. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  114. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  115. };
  116. const struct ctrl_ioregs ioregs_igep0034_lite = {
  117. .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  118. .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  119. .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  120. .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  121. .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  122. };
  123. #define OSC (V_OSCK/1000000)
  124. const struct dpll_params dpll_ddr = {
  125. 400, OSC-1, 1, -1, -1, -1, -1};
  126. const struct dpll_params *get_dpll_ddr_params(void)
  127. {
  128. return &dpll_ddr;
  129. }
  130. void set_uart_mux_conf(void)
  131. {
  132. enable_uart0_pin_mux();
  133. }
  134. void set_mux_conf_regs(void)
  135. {
  136. enable_board_pin_mux();
  137. }
  138. void sdram_init(void)
  139. {
  140. if (get_board_revision() == 1)
  141. config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
  142. &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
  143. else
  144. config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
  145. &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
  146. }
  147. #ifdef CONFIG_SPL_OS_BOOT
  148. int spl_start_uboot(void)
  149. {
  150. /* break into full u-boot on 'c' */
  151. return serial_tstc() && serial_getc() == 'c';
  152. }
  153. #endif
  154. #endif
  155. /*
  156. * Basic board specific setup. Pinmux has been handled already.
  157. */
  158. int board_init(void)
  159. {
  160. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  161. gpmc_init();
  162. return 0;
  163. }
  164. #ifdef CONFIG_BOARD_LATE_INIT
  165. int board_late_init(void)
  166. {
  167. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  168. switch (get_board_revision()) {
  169. case 0:
  170. env_set("board_name", "igep0034-lite");
  171. break;
  172. case 1:
  173. env_set("board_name", "igep0034");
  174. break;
  175. default:
  176. env_set("board_name", "igep0033");
  177. break;
  178. }
  179. #endif
  180. return 0;
  181. }
  182. #endif
  183. #ifdef CONFIG_OF_BOARD_SETUP
  184. int ft_board_setup(void *blob, struct bd_info *bd)
  185. {
  186. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  187. static const struct node_info nodes[] = {
  188. { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
  189. };
  190. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  191. #endif
  192. return 0;
  193. }
  194. #endif
  195. #if defined(CONFIG_DRIVER_TI_CPSW)
  196. static void cpsw_control(int enabled)
  197. {
  198. /* VTP can be added here */
  199. return;
  200. }
  201. static struct cpsw_slave_data cpsw_slaves[] = {
  202. {
  203. .slave_reg_ofs = 0x208,
  204. .sliver_reg_ofs = 0xd80,
  205. .phy_addr = 0,
  206. .phy_if = PHY_INTERFACE_MODE_RMII,
  207. },
  208. };
  209. static struct cpsw_platform_data cpsw_data = {
  210. .mdio_base = CPSW_MDIO_BASE,
  211. .cpsw_base = CPSW_BASE,
  212. .mdio_div = 0xff,
  213. .channels = 8,
  214. .cpdma_reg_ofs = 0x800,
  215. .slaves = 1,
  216. .slave_data = cpsw_slaves,
  217. .ale_reg_ofs = 0xd00,
  218. .ale_entries = 1024,
  219. .host_port_reg_ofs = 0x108,
  220. .hw_stats_reg_ofs = 0x900,
  221. .bd_ram_ofs = 0x2000,
  222. .mac_control = (1 << 5),
  223. .control = cpsw_control,
  224. .host_port_num = 0,
  225. .version = CPSW_CTRL_VERSION_2,
  226. };
  227. int board_eth_init(struct bd_info *bis)
  228. {
  229. int rv, ret = 0;
  230. uint8_t mac_addr[6];
  231. uint32_t mac_hi, mac_lo;
  232. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  233. /* try reading mac address from efuse */
  234. mac_lo = readl(&cdev->macid0l);
  235. mac_hi = readl(&cdev->macid0h);
  236. mac_addr[0] = mac_hi & 0xFF;
  237. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  238. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  239. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  240. mac_addr[4] = mac_lo & 0xFF;
  241. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  242. if (is_valid_ethaddr(mac_addr))
  243. eth_env_set_enetaddr("ethaddr", mac_addr);
  244. }
  245. writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
  246. &cdev->miisel);
  247. if (get_board_revision() == 1)
  248. cpsw_slaves[0].phy_addr = 1;
  249. rv = cpsw_register(&cpsw_data);
  250. if (rv < 0)
  251. printf("Error %d registering CPSW switch\n", rv);
  252. else
  253. ret += rv;
  254. return ret;
  255. }
  256. #endif