variant_gpio.h 1.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2019 Google LLC
  4. *
  5. * Taken from coreboot file of the same name
  6. */
  7. #ifndef BASEBOARD_GPIO_H
  8. #define BASEBOARD_GPIO_H
  9. #include <asm/arch/gpio.h>
  10. #include <ec_commands.h>
  11. /*
  12. * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
  13. * which is North community
  14. */
  15. #define EC_SCI_GPI GPE0_DW1_11
  16. /* EC SMI */
  17. #define EC_SMI_GPI GPIO_49
  18. /*
  19. * On lidopen/lidclose GPIO_22 from North Community gets toggled and
  20. * is used in _PRW to wake up device from sleep. GPIO_22 maps to
  21. * group GPIO_GPE_N_31_0 and the pad is configured as SCI with
  22. * EDGE_SINGLE and INVERT.
  23. */
  24. #define GPE_EC_WAKE GPE0_DW1_22
  25. /* Write Protect and indication if EC is in RW code. */
  26. #define GPIO_PCH_WP GPIO_75
  27. #define GPIO_EC_IN_RW GPIO_41
  28. /* Determine if board is in final shipping mode. */
  29. #define GPIO_SHIP_MODE GPIO_10
  30. /* Memory SKU GPIOs. */
  31. #define MEM_CONFIG3 GPIO_45
  32. #define MEM_CONFIG2 GPIO_38
  33. #define MEM_CONFIG1 GPIO_102
  34. #define MEM_CONFIG0 GPIO_101
  35. /* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */
  36. #define DMIC_CONFIG_PIN GPIO_17
  37. #ifndef __ASSEMBLY__
  38. enum cros_gpio_t {
  39. CROS_GPIO_REC = 1, /* Recovery */
  40. /* Developer; * deprecated (chromium:942901) */
  41. CROS_GPIO_DEPRECATED_DEV = 2,
  42. CROS_GPIO_WP = 3, /* Write Protect */
  43. CROS_GPIO_PE = 4, /* Phase enforcement for final product */
  44. CROS_GPIO_ACTIVE_LOW = 0,
  45. CROS_GPIO_ACTIVE_HIGH = 1,
  46. CROS_GPIO_VIRTUAL = -1,
  47. };
  48. #endif
  49. #endif /* BASEBOARD_GPIO_H */