diu.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. * Authors: Timur Tabi <timur@freescale.com>
  5. *
  6. * FSL DIU Framebuffer driver
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <command.h>
  11. #include <log.h>
  12. #include <linux/ctype.h>
  13. #include <asm/io.h>
  14. #include <stdio_dev.h>
  15. #include <video_fb.h>
  16. #include <fsl_diu_fb.h>
  17. #define PMUXCR_ELBCDIU_MASK 0xc0000000
  18. #define PMUXCR_ELBCDIU_NOR16 0x80000000
  19. #define PMUXCR_ELBCDIU_DIU 0x40000000
  20. /*
  21. * DIU Area Descriptor
  22. *
  23. * Note that we need to byte-swap the value before it's written to the AD
  24. * register. So even though the registers don't look like they're in the same
  25. * bit positions as they are on the MPC8610, the same value is written to the
  26. * AD register on the MPC8610 and on the P1022.
  27. */
  28. #define AD_BYTE_F 0x10000000
  29. #define AD_ALPHA_C_SHIFT 25
  30. #define AD_BLUE_C_SHIFT 23
  31. #define AD_GREEN_C_SHIFT 21
  32. #define AD_RED_C_SHIFT 19
  33. #define AD_PIXEL_S_SHIFT 16
  34. #define AD_COMP_3_SHIFT 12
  35. #define AD_COMP_2_SHIFT 8
  36. #define AD_COMP_1_SHIFT 4
  37. #define AD_COMP_0_SHIFT 0
  38. /*
  39. * Variables used by the DIU/LBC switching code. It's safe to makes these
  40. * global, because the DIU requires DDR, so we'll only run this code after
  41. * relocation.
  42. */
  43. static u32 pmuxcr;
  44. void diu_set_pixel_clock(unsigned int pixclock)
  45. {
  46. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  47. unsigned long speed_ccb, temp;
  48. u32 pixval;
  49. speed_ccb = get_bus_freq(0);
  50. temp = 1000000000 / pixclock;
  51. temp *= 1000;
  52. pixval = speed_ccb / temp;
  53. debug("DIU pixval = %u\n", pixval);
  54. /* Modify PXCLK in GUTS CLKDVDR */
  55. temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
  56. out_be32(&gur->clkdvdr, temp); /* turn off clock */
  57. out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
  58. }
  59. int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
  60. {
  61. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  62. u32 pixel_format;
  63. pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
  64. (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
  65. (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
  66. (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
  67. (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
  68. printf("DIU: Switching to %ux%u\n", xres, yres);
  69. /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
  70. clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
  71. pmuxcr = in_be32(&gur->pmuxcr);
  72. return fsl_diu_init(xres, yres, pixel_format, 0);
  73. }