strider.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <flash.h>
  9. #include <hwconfig.h>
  10. #include <i2c.h>
  11. #include <init.h>
  12. #include <spi.h>
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. #include <linux/libfdt.h>
  16. #include <fdt_support.h>
  17. #include <pci.h>
  18. #include <mpc83xx.h>
  19. #include <fsl_esdhc.h>
  20. #include <asm/io.h>
  21. #include <asm/fsl_serdes.h>
  22. #include <asm/fsl_mpc83xx_serdes.h>
  23. #include "mpc8308.h"
  24. #include <gdsys_fpga.h>
  25. #include "../common/adv7611.h"
  26. #include "../common/ch7301.h"
  27. #include "../common/dp501.h"
  28. #include "../common/ioep-fpga.h"
  29. #include "../common/mclink.h"
  30. #include "../common/osd.h"
  31. #include "../common/phy.h"
  32. #include "../common/fanctrl.h"
  33. #include <pca953x.h>
  34. #include <pca9698.h>
  35. #include <miiphy.h>
  36. #define MAX_MUX_CHANNELS 2
  37. enum {
  38. MCFPGA_DONE = 1 << 0,
  39. MCFPGA_INIT_N = 1 << 1,
  40. MCFPGA_PROGRAM_N = 1 << 2,
  41. MCFPGA_UPDATE_ENABLE_N = 1 << 3,
  42. MCFPGA_RESET_N = 1 << 4,
  43. };
  44. enum {
  45. GPIO_MDC = 1 << 14,
  46. GPIO_MDIO = 1 << 15,
  47. };
  48. uint mclink_fpgacount;
  49. struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  50. struct {
  51. u8 bus;
  52. u8 addr;
  53. } strider_fans[] = CONFIG_STRIDER_FANS;
  54. int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
  55. {
  56. int res;
  57. switch (fpga) {
  58. case 0:
  59. out_le16(reg, data);
  60. break;
  61. default:
  62. res = mclink_send(fpga - 1, regoff, data);
  63. if (res < 0) {
  64. printf("mclink_send reg %02lx data %04x returned %d\n",
  65. regoff, data, res);
  66. return res;
  67. }
  68. break;
  69. }
  70. return 0;
  71. }
  72. int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
  73. {
  74. int res;
  75. switch (fpga) {
  76. case 0:
  77. *data = in_le16(reg);
  78. break;
  79. default:
  80. if (fpga > mclink_fpgacount)
  81. return -EINVAL;
  82. res = mclink_receive(fpga - 1, regoff, data);
  83. if (res < 0) {
  84. printf("mclink_receive reg %02lx returned %d\n",
  85. regoff, res);
  86. return res;
  87. }
  88. }
  89. return 0;
  90. }
  91. int checkboard(void)
  92. {
  93. char *s = env_get("serial#");
  94. bool hw_type_cat = pca9698_get_value(0x20, 18);
  95. puts("Board: ");
  96. printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
  97. if (s) {
  98. puts(", serial# ");
  99. puts(s);
  100. }
  101. puts("\n");
  102. return 0;
  103. }
  104. int last_stage_init(void)
  105. {
  106. int slaves;
  107. uint k;
  108. uint mux_ch;
  109. uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
  110. #ifdef CONFIG_STRIDER_CPU
  111. uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
  112. #endif
  113. bool hw_type_cat = pca9698_get_value(0x20, 18);
  114. #ifdef CONFIG_STRIDER_CON_DP
  115. bool is_dh = pca9698_get_value(0x20, 25);
  116. #endif
  117. bool ch0_sgmii2_present;
  118. /* Turn on Analog Devices ADV7611 */
  119. pca9698_direction_output(0x20, 8, 0);
  120. /* Turn on Parade DP501 */
  121. pca9698_direction_output(0x20, 10, 1);
  122. pca9698_direction_output(0x20, 11, 1);
  123. ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
  124. /* wait for FPGA done, then reset FPGA */
  125. for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
  126. uint ctr = 0;
  127. uchar *mclink_controllers = mclink_controllers_dvi;
  128. #ifdef CONFIG_STRIDER_CPU
  129. if (i2c_probe(mclink_controllers[k])) {
  130. mclink_controllers = mclink_controllers_dp;
  131. if (i2c_probe(mclink_controllers[k]))
  132. continue;
  133. }
  134. #else
  135. if (i2c_probe(mclink_controllers[k]))
  136. continue;
  137. #endif
  138. while (!(pca953x_get_val(mclink_controllers[k])
  139. & MCFPGA_DONE)) {
  140. mdelay(100);
  141. if (ctr++ > 5) {
  142. printf("no done for mclink_controller %d\n", k);
  143. break;
  144. }
  145. }
  146. pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
  147. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
  148. udelay(10);
  149. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
  150. MCFPGA_RESET_N);
  151. }
  152. if (hw_type_cat) {
  153. int retval;
  154. struct mii_dev *mdiodev = mdio_alloc();
  155. if (!mdiodev)
  156. return -ENOMEM;
  157. strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
  158. mdiodev->read = bb_miiphy_read;
  159. mdiodev->write = bb_miiphy_write;
  160. retval = mdio_register(mdiodev);
  161. if (retval < 0)
  162. return retval;
  163. for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
  164. if ((mux_ch == 1) && !ch0_sgmii2_present)
  165. continue;
  166. setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
  167. }
  168. }
  169. /* give slave-PLLs and Parade DP501 some time to be up and running */
  170. mdelay(500);
  171. mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
  172. slaves = mclink_probe();
  173. mclink_fpgacount = 0;
  174. ioep_fpga_print_info(0);
  175. if (!adv7611_probe(0))
  176. printf(" Advantiv ADV7611 HDMI Receiver\n");
  177. #ifdef CONFIG_STRIDER_CON
  178. if (ioep_fpga_has_osd(0))
  179. osd_probe(0);
  180. #endif
  181. #ifdef CONFIG_STRIDER_CON_DP
  182. if (ioep_fpga_has_osd(0)) {
  183. osd_probe(0);
  184. if (is_dh)
  185. osd_probe(4);
  186. }
  187. #endif
  188. #ifdef CONFIG_STRIDER_CPU
  189. ch7301_probe(0, false);
  190. dp501_probe(0, false);
  191. #endif
  192. if (slaves <= 0)
  193. return 0;
  194. mclink_fpgacount = slaves;
  195. #ifdef CONFIG_STRIDER_CPU
  196. /* get ADV7611 out of reset, power up DP501, give some time to wakeup */
  197. for (k = 1; k <= slaves; ++k)
  198. FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
  199. mdelay(500);
  200. #endif
  201. for (k = 1; k <= slaves; ++k) {
  202. ioep_fpga_print_info(k);
  203. #ifdef CONFIG_STRIDER_CON
  204. if (ioep_fpga_has_osd(k))
  205. osd_probe(k);
  206. #endif
  207. #ifdef CONFIG_STRIDER_CON_DP
  208. if (ioep_fpga_has_osd(k)) {
  209. osd_probe(k);
  210. if (is_dh)
  211. osd_probe(k + 4);
  212. }
  213. #endif
  214. #ifdef CONFIG_STRIDER_CPU
  215. if (!adv7611_probe(k))
  216. printf(" Advantiv ADV7611 HDMI Receiver\n");
  217. ch7301_probe(k, false);
  218. dp501_probe(k, false);
  219. #endif
  220. if (hw_type_cat) {
  221. int retval;
  222. struct mii_dev *mdiodev = mdio_alloc();
  223. if (!mdiodev)
  224. return -ENOMEM;
  225. strncpy(mdiodev->name, bb_miiphy_buses[k].name,
  226. MDIO_NAME_LEN);
  227. mdiodev->read = bb_miiphy_read;
  228. mdiodev->write = bb_miiphy_write;
  229. retval = mdio_register(mdiodev);
  230. if (retval < 0)
  231. return retval;
  232. setup_88e1514(bb_miiphy_buses[k].name, 0);
  233. }
  234. }
  235. for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
  236. i2c_set_bus_num(strider_fans[k].bus);
  237. init_fan_controller(strider_fans[k].addr);
  238. }
  239. return 0;
  240. }
  241. /*
  242. * provide access to fpga gpios (for I2C bitbang)
  243. * (these may look all too simple but make iocon.h much more readable)
  244. */
  245. void fpga_gpio_set(uint bus, int pin)
  246. {
  247. FPGA_SET_REG(bus, gpio.set, pin);
  248. }
  249. void fpga_gpio_clear(uint bus, int pin)
  250. {
  251. FPGA_SET_REG(bus, gpio.clear, pin);
  252. }
  253. int fpga_gpio_get(uint bus, int pin)
  254. {
  255. u16 val;
  256. FPGA_GET_REG(bus, gpio.read, &val);
  257. return val & pin;
  258. }
  259. #ifdef CONFIG_STRIDER_CON_DP
  260. void fpga_control_set(uint bus, int pin)
  261. {
  262. u16 val;
  263. FPGA_GET_REG(bus, control, &val);
  264. FPGA_SET_REG(bus, control, val | pin);
  265. }
  266. void fpga_control_clear(uint bus, int pin)
  267. {
  268. u16 val;
  269. FPGA_GET_REG(bus, control, &val);
  270. FPGA_SET_REG(bus, control, val & ~pin);
  271. }
  272. #endif
  273. void mpc8308_init(void)
  274. {
  275. pca9698_direction_output(0x20, 26, 1);
  276. }
  277. void mpc8308_set_fpga_reset(uint state)
  278. {
  279. pca9698_set_value(0x20, 26, state ? 0 : 1);
  280. }
  281. void mpc8308_setup_hw(void)
  282. {
  283. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  284. /*
  285. * set "startup-finished"-gpios
  286. */
  287. setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
  288. setbits_gpio0_out(BIT(31 - 12));
  289. }
  290. int mpc8308_get_fpga_done(uint fpga)
  291. {
  292. return pca9698_get_value(0x20, 20);
  293. }
  294. #ifdef CONFIG_FSL_ESDHC
  295. int board_mmc_init(struct bd_info *bd)
  296. {
  297. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  298. sysconf83xx_t *sysconf = &immr->sysconf;
  299. /* Enable cache snooping in eSDHC system configuration register */
  300. out_be32(&sysconf->sdhccr, 0x02000000);
  301. return fsl_esdhc_mmc_init(bd);
  302. }
  303. #endif
  304. static struct pci_region pcie_regions_0[] = {
  305. {
  306. .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  307. .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  308. .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  309. .flags = PCI_REGION_MEM,
  310. },
  311. {
  312. .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  313. .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  314. .size = CONFIG_SYS_PCIE1_IO_SIZE,
  315. .flags = PCI_REGION_IO,
  316. },
  317. };
  318. void pci_init_board(void)
  319. {
  320. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  321. sysconf83xx_t *sysconf = &immr->sysconf;
  322. law83xx_t *pcie_law = sysconf->pcielaw;
  323. struct pci_region *pcie_reg[] = { pcie_regions_0 };
  324. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
  325. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  326. /* Deassert the resets in the control register */
  327. out_be32(&sysconf->pecr1, 0xE0008000);
  328. udelay(2000);
  329. /* Configure PCI Express Local Access Windows */
  330. out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  331. out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  332. mpc83xx_pcie_init(1, pcie_reg);
  333. }
  334. ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
  335. {
  336. info->portwidth = FLASH_CFI_16BIT;
  337. info->chipwidth = FLASH_CFI_BY16;
  338. info->interface = FLASH_CFI_X16;
  339. return 1;
  340. }
  341. #if defined(CONFIG_OF_BOARD_SETUP)
  342. int ft_board_setup(void *blob, struct bd_info *bd)
  343. {
  344. ft_cpu_setup(blob, bd);
  345. fsl_fdt_fixup_dr_usb(blob, bd);
  346. fdt_fixup_esdhc(blob, bd);
  347. return 0;
  348. }
  349. #endif
  350. /*
  351. * FPGA MII bitbang implementation
  352. */
  353. struct fpga_mii {
  354. uint fpga;
  355. int mdio;
  356. } fpga_mii[] = {
  357. { 0, 1},
  358. { 1, 1},
  359. { 2, 1},
  360. { 3, 1},
  361. };
  362. static int mii_dummy_init(struct bb_miiphy_bus *bus)
  363. {
  364. return 0;
  365. }
  366. static int mii_mdio_active(struct bb_miiphy_bus *bus)
  367. {
  368. struct fpga_mii *fpga_mii = bus->priv;
  369. if (fpga_mii->mdio)
  370. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  371. else
  372. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  373. return 0;
  374. }
  375. static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
  376. {
  377. struct fpga_mii *fpga_mii = bus->priv;
  378. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  379. return 0;
  380. }
  381. static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
  382. {
  383. struct fpga_mii *fpga_mii = bus->priv;
  384. if (v)
  385. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  386. else
  387. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  388. fpga_mii->mdio = v;
  389. return 0;
  390. }
  391. static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
  392. {
  393. u16 gpio;
  394. struct fpga_mii *fpga_mii = bus->priv;
  395. FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
  396. *v = ((gpio & GPIO_MDIO) != 0);
  397. return 0;
  398. }
  399. static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
  400. {
  401. struct fpga_mii *fpga_mii = bus->priv;
  402. if (v)
  403. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
  404. else
  405. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
  406. return 0;
  407. }
  408. static int mii_delay(struct bb_miiphy_bus *bus)
  409. {
  410. udelay(1);
  411. return 0;
  412. }
  413. struct bb_miiphy_bus bb_miiphy_buses[] = {
  414. {
  415. .name = "board0",
  416. .init = mii_dummy_init,
  417. .mdio_active = mii_mdio_active,
  418. .mdio_tristate = mii_mdio_tristate,
  419. .set_mdio = mii_set_mdio,
  420. .get_mdio = mii_get_mdio,
  421. .set_mdc = mii_set_mdc,
  422. .delay = mii_delay,
  423. .priv = &fpga_mii[0],
  424. },
  425. {
  426. .name = "board1",
  427. .init = mii_dummy_init,
  428. .mdio_active = mii_mdio_active,
  429. .mdio_tristate = mii_mdio_tristate,
  430. .set_mdio = mii_set_mdio,
  431. .get_mdio = mii_get_mdio,
  432. .set_mdc = mii_set_mdc,
  433. .delay = mii_delay,
  434. .priv = &fpga_mii[1],
  435. },
  436. {
  437. .name = "board2",
  438. .init = mii_dummy_init,
  439. .mdio_active = mii_mdio_active,
  440. .mdio_tristate = mii_mdio_tristate,
  441. .set_mdio = mii_set_mdio,
  442. .get_mdio = mii_get_mdio,
  443. .set_mdc = mii_set_mdc,
  444. .delay = mii_delay,
  445. .priv = &fpga_mii[2],
  446. },
  447. {
  448. .name = "board3",
  449. .init = mii_dummy_init,
  450. .mdio_active = mii_mdio_active,
  451. .mdio_tristate = mii_mdio_tristate,
  452. .set_mdio = mii_set_mdio,
  453. .get_mdio = mii_get_mdio,
  454. .set_mdc = mii_set_mdc,
  455. .delay = mii_delay,
  456. .priv = &fpga_mii[3],
  457. },
  458. };
  459. int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);