eth_t208xqds.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. *
  6. * Shengzhou Liu <Shengzhou.Liu@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <fdt_support.h>
  11. #include <log.h>
  12. #include <net.h>
  13. #include <netdev.h>
  14. #include <asm/mmu.h>
  15. #include <asm/processor.h>
  16. #include <asm/immap_85xx.h>
  17. #include <asm/fsl_law.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_portals.h>
  20. #include <asm/fsl_liodn.h>
  21. #include <malloc.h>
  22. #include <fm_eth.h>
  23. #include <fsl_mdio.h>
  24. #include <miiphy.h>
  25. #include <phy.h>
  26. #include <fsl_dtsec.h>
  27. #include <asm/fsl_serdes.h>
  28. #include <hwconfig.h>
  29. #include "../common/qixis.h"
  30. #include "../common/fman.h"
  31. #include "t208xqds_qixis.h"
  32. #include <linux/libfdt.h>
  33. #define EMI_NONE 0xFFFFFFFF
  34. #define EMI1_RGMII1 0
  35. #define EMI1_RGMII2 1
  36. #define EMI1_SLOT1 2
  37. #if defined(CONFIG_TARGET_T2080QDS)
  38. #define EMI1_SLOT2 6
  39. #define EMI1_SLOT3 3
  40. #define EMI1_SLOT4 4
  41. #define EMI1_SLOT5 5
  42. #define EMI2 7
  43. #elif defined(CONFIG_TARGET_T2081QDS)
  44. #define EMI1_SLOT2 3
  45. #define EMI1_SLOT3 4
  46. #define EMI1_SLOT5 5
  47. #define EMI1_SLOT6 6
  48. #define EMI1_SLOT7 7
  49. #define EMI2 8
  50. #endif
  51. #define PCCR1_SGMIIA_KX_MASK 0x00008000
  52. #define PCCR1_SGMIIB_KX_MASK 0x00004000
  53. #define PCCR1_SGMIIC_KX_MASK 0x00002000
  54. #define PCCR1_SGMIID_KX_MASK 0x00001000
  55. #define PCCR1_SGMIIE_KX_MASK 0x00000800
  56. #define PCCR1_SGMIIF_KX_MASK 0x00000400
  57. #define PCCR1_SGMIIG_KX_MASK 0x00000200
  58. #define PCCR1_SGMIIH_KX_MASK 0x00000100
  59. static int mdio_mux[NUM_FM_PORTS];
  60. static const char * const mdio_names[] = {
  61. #if defined(CONFIG_TARGET_T2080QDS)
  62. "T2080QDS_MDIO_RGMII1",
  63. "T2080QDS_MDIO_RGMII2",
  64. "T2080QDS_MDIO_SLOT1",
  65. "T2080QDS_MDIO_SLOT3",
  66. "T2080QDS_MDIO_SLOT4",
  67. "T2080QDS_MDIO_SLOT5",
  68. "T2080QDS_MDIO_SLOT2",
  69. "T2080QDS_MDIO_10GC",
  70. #elif defined(CONFIG_TARGET_T2081QDS)
  71. "T2081QDS_MDIO_RGMII1",
  72. "T2081QDS_MDIO_RGMII2",
  73. "T2081QDS_MDIO_SLOT1",
  74. "T2081QDS_MDIO_SLOT2",
  75. "T2081QDS_MDIO_SLOT3",
  76. "T2081QDS_MDIO_SLOT5",
  77. "T2081QDS_MDIO_SLOT6",
  78. "T2081QDS_MDIO_SLOT7",
  79. "T2081QDS_MDIO_10GC",
  80. #endif
  81. };
  82. /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
  83. #if defined(CONFIG_TARGET_T2080QDS)
  84. static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
  85. #elif defined(CONFIG_TARGET_T2081QDS)
  86. static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
  87. #endif
  88. static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
  89. {
  90. return mdio_names[muxval];
  91. }
  92. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  93. {
  94. struct mii_dev *bus;
  95. const char *name = t208xqds_mdio_name_for_muxval(muxval);
  96. if (!name) {
  97. printf("No bus for muxval %x\n", muxval);
  98. return NULL;
  99. }
  100. bus = miiphy_get_dev_by_name(name);
  101. if (!bus) {
  102. printf("No bus by name %s\n", name);
  103. return NULL;
  104. }
  105. return bus;
  106. }
  107. struct t208xqds_mdio {
  108. u8 muxval;
  109. struct mii_dev *realbus;
  110. };
  111. static void t208xqds_mux_mdio(u8 muxval)
  112. {
  113. u8 brdcfg4;
  114. if (muxval < 8) {
  115. brdcfg4 = QIXIS_READ(brdcfg[4]);
  116. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  117. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  118. QIXIS_WRITE(brdcfg[4], brdcfg4);
  119. }
  120. }
  121. static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
  122. int regnum)
  123. {
  124. struct t208xqds_mdio *priv = bus->priv;
  125. t208xqds_mux_mdio(priv->muxval);
  126. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  127. }
  128. static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
  129. int regnum, u16 value)
  130. {
  131. struct t208xqds_mdio *priv = bus->priv;
  132. t208xqds_mux_mdio(priv->muxval);
  133. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  134. }
  135. static int t208xqds_mdio_reset(struct mii_dev *bus)
  136. {
  137. struct t208xqds_mdio *priv = bus->priv;
  138. return priv->realbus->reset(priv->realbus);
  139. }
  140. static int t208xqds_mdio_init(char *realbusname, u8 muxval)
  141. {
  142. struct t208xqds_mdio *pmdio;
  143. struct mii_dev *bus = mdio_alloc();
  144. if (!bus) {
  145. printf("Failed to allocate t208xqds MDIO bus\n");
  146. return -1;
  147. }
  148. pmdio = malloc(sizeof(*pmdio));
  149. if (!pmdio) {
  150. printf("Failed to allocate t208xqds private data\n");
  151. free(bus);
  152. return -1;
  153. }
  154. bus->read = t208xqds_mdio_read;
  155. bus->write = t208xqds_mdio_write;
  156. bus->reset = t208xqds_mdio_reset;
  157. strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
  158. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  159. if (!pmdio->realbus) {
  160. printf("No bus with name %s\n", realbusname);
  161. free(bus);
  162. free(pmdio);
  163. return -1;
  164. }
  165. pmdio->muxval = muxval;
  166. bus->priv = pmdio;
  167. return mdio_register(bus);
  168. }
  169. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  170. enum fm_port port, int offset)
  171. {
  172. int phy;
  173. char alias[20];
  174. char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
  175. char buf[32] = "serdes-1,";
  176. struct fixed_link f_link;
  177. int media_type = 0;
  178. const char *phyconn;
  179. int off;
  180. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  181. #ifdef CONFIG_TARGET_T2080QDS
  182. serdes_corenet_t *srds_regs =
  183. (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  184. u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
  185. #endif
  186. u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
  187. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  188. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  189. if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  190. phy = fm_info_get_phy_address(port);
  191. switch (port) {
  192. #if defined(CONFIG_TARGET_T2080QDS)
  193. case FM1_DTSEC1:
  194. if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
  195. media_type = 1;
  196. fdt_set_phy_handle(fdt, compat, addr,
  197. "phy_1gkx1");
  198. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
  199. sprintf(buf, "%s%s%s", buf, "lane-c,",
  200. (char *)lane_mode[0]);
  201. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  202. PCCR1_SGMIIH_KX_MASK);
  203. break;
  204. }
  205. case FM1_DTSEC2:
  206. if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
  207. media_type = 1;
  208. fdt_set_phy_handle(fdt, compat, addr,
  209. "phy_1gkx2");
  210. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
  211. sprintf(buf, "%s%s%s", buf, "lane-d,",
  212. (char *)lane_mode[0]);
  213. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  214. PCCR1_SGMIIG_KX_MASK);
  215. break;
  216. }
  217. case FM1_DTSEC9:
  218. if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
  219. media_type = 1;
  220. fdt_set_phy_handle(fdt, compat, addr,
  221. "phy_1gkx9");
  222. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
  223. sprintf(buf, "%s%s%s", buf, "lane-a,",
  224. (char *)lane_mode[0]);
  225. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  226. PCCR1_SGMIIE_KX_MASK);
  227. break;
  228. }
  229. case FM1_DTSEC10:
  230. if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
  231. media_type = 1;
  232. fdt_set_phy_handle(fdt, compat, addr,
  233. "phy_1gkx10");
  234. fdt_status_okay_by_alias(fdt,
  235. "1gkx_pcs_mdio10");
  236. sprintf(buf, "%s%s%s", buf, "lane-b,",
  237. (char *)lane_mode[0]);
  238. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  239. PCCR1_SGMIIF_KX_MASK);
  240. break;
  241. }
  242. if (mdio_mux[port] == EMI1_SLOT2) {
  243. sprintf(alias, "phy_sgmii_s2_%x", phy);
  244. fdt_set_phy_handle(fdt, compat, addr, alias);
  245. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  246. } else if (mdio_mux[port] == EMI1_SLOT3) {
  247. sprintf(alias, "phy_sgmii_s3_%x", phy);
  248. fdt_set_phy_handle(fdt, compat, addr, alias);
  249. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  250. }
  251. break;
  252. case FM1_DTSEC5:
  253. if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
  254. media_type = 1;
  255. fdt_set_phy_handle(fdt, compat, addr,
  256. "phy_1gkx5");
  257. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
  258. sprintf(buf, "%s%s%s", buf, "lane-g,",
  259. (char *)lane_mode[0]);
  260. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  261. PCCR1_SGMIIC_KX_MASK);
  262. break;
  263. }
  264. case FM1_DTSEC6:
  265. if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
  266. media_type = 1;
  267. fdt_set_phy_handle(fdt, compat, addr,
  268. "phy_1gkx6");
  269. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
  270. sprintf(buf, "%s%s%s", buf, "lane-h,",
  271. (char *)lane_mode[0]);
  272. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  273. PCCR1_SGMIID_KX_MASK);
  274. break;
  275. }
  276. if (mdio_mux[port] == EMI1_SLOT1) {
  277. sprintf(alias, "phy_sgmii_s1_%x", phy);
  278. fdt_set_phy_handle(fdt, compat, addr, alias);
  279. fdt_status_okay_by_alias(fdt, "emi1_slot1");
  280. } else if (mdio_mux[port] == EMI1_SLOT2) {
  281. sprintf(alias, "phy_sgmii_s2_%x", phy);
  282. fdt_set_phy_handle(fdt, compat, addr, alias);
  283. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  284. }
  285. break;
  286. #elif defined(CONFIG_TARGET_T2081QDS)
  287. case FM1_DTSEC1:
  288. case FM1_DTSEC2:
  289. case FM1_DTSEC5:
  290. case FM1_DTSEC6:
  291. case FM1_DTSEC9:
  292. case FM1_DTSEC10:
  293. if (mdio_mux[port] == EMI1_SLOT2) {
  294. sprintf(alias, "phy_sgmii_s2_%x", phy);
  295. fdt_set_phy_handle(fdt, compat, addr, alias);
  296. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  297. } else if (mdio_mux[port] == EMI1_SLOT3) {
  298. sprintf(alias, "phy_sgmii_s3_%x", phy);
  299. fdt_set_phy_handle(fdt, compat, addr, alias);
  300. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  301. } else if (mdio_mux[port] == EMI1_SLOT5) {
  302. sprintf(alias, "phy_sgmii_s5_%x", phy);
  303. fdt_set_phy_handle(fdt, compat, addr, alias);
  304. fdt_status_okay_by_alias(fdt, "emi1_slot5");
  305. } else if (mdio_mux[port] == EMI1_SLOT6) {
  306. sprintf(alias, "phy_sgmii_s6_%x", phy);
  307. fdt_set_phy_handle(fdt, compat, addr, alias);
  308. fdt_status_okay_by_alias(fdt, "emi1_slot6");
  309. } else if (mdio_mux[port] == EMI1_SLOT7) {
  310. sprintf(alias, "phy_sgmii_s7_%x", phy);
  311. fdt_set_phy_handle(fdt, compat, addr, alias);
  312. fdt_status_okay_by_alias(fdt, "emi1_slot7");
  313. }
  314. break;
  315. #endif
  316. default:
  317. break;
  318. }
  319. if (media_type) {
  320. /* set property for 1000BASE-KX in dtb */
  321. off = fdt_node_offset_by_compat_reg(fdt,
  322. "fsl,fman-memac-mdio", addr + 0x1000);
  323. fdt_setprop_string(fdt, off, "lane-instance", buf);
  324. }
  325. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
  326. switch (srds_s1) {
  327. case 0x66: /* XFI interface */
  328. case 0x6b:
  329. case 0x6c:
  330. case 0x6d:
  331. case 0x71:
  332. /*
  333. * if the 10G is XFI, check hwconfig to see what is the
  334. * media type, there are two types, fiber or copper,
  335. * fix the dtb accordingly.
  336. */
  337. switch (port) {
  338. case FM1_10GEC1:
  339. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
  340. /* it's MAC9 */
  341. media_type = 1;
  342. fdt_set_phy_handle(fdt, compat, addr,
  343. "phy_xfi9");
  344. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
  345. sprintf(buf, "%s%s%s", buf, "lane-a,",
  346. (char *)lane_mode[1]);
  347. }
  348. break;
  349. case FM1_10GEC2:
  350. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
  351. /* it's MAC10 */
  352. media_type = 1;
  353. fdt_set_phy_handle(fdt, compat, addr,
  354. "phy_xfi10");
  355. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
  356. sprintf(buf, "%s%s%s", buf, "lane-b,",
  357. (char *)lane_mode[1]);
  358. }
  359. break;
  360. case FM1_10GEC3:
  361. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
  362. /* it's MAC1 */
  363. media_type = 1;
  364. fdt_set_phy_handle(fdt, compat, addr,
  365. "phy_xfi1");
  366. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
  367. sprintf(buf, "%s%s%s", buf, "lane-c,",
  368. (char *)lane_mode[1]);
  369. }
  370. break;
  371. case FM1_10GEC4:
  372. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
  373. /* it's MAC2 */
  374. media_type = 1;
  375. fdt_set_phy_handle(fdt, compat, addr,
  376. "phy_xfi2");
  377. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
  378. sprintf(buf, "%s%s%s", buf, "lane-d,",
  379. (char *)lane_mode[1]);
  380. }
  381. break;
  382. default:
  383. return;
  384. }
  385. if (!media_type) {
  386. phyconn = fdt_getprop(fdt, offset,
  387. "phy-connection-type",
  388. NULL);
  389. if (is_backplane_mode(phyconn)) {
  390. /* Backplane KR mode: skip fixups */
  391. printf("Interface %d in backplane KR mode\n",
  392. port);
  393. } else {
  394. /* fixed-link for XFI fiber cable */
  395. f_link.phy_id = port;
  396. f_link.duplex = 1;
  397. f_link.link_speed = 10000;
  398. f_link.pause = 0;
  399. f_link.asym_pause = 0;
  400. fdt_delprop(fdt, offset, "phy-handle");
  401. fdt_setprop(fdt, offset, "fixed-link",
  402. &f_link, sizeof(f_link));
  403. }
  404. } else {
  405. /* set property for copper cable */
  406. off = fdt_node_offset_by_compat_reg(fdt,
  407. "fsl,fman-memac-mdio", addr + 0x1000);
  408. fdt_setprop_string(fdt, off,
  409. "lane-instance", buf);
  410. }
  411. break;
  412. default:
  413. break;
  414. }
  415. }
  416. }
  417. void fdt_fixup_board_enet(void *fdt)
  418. {
  419. return;
  420. }
  421. /*
  422. * This function reads RCW to check if Serdes1{A:H} is configured
  423. * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
  424. */
  425. static void initialize_lane_to_slot(void)
  426. {
  427. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  428. u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
  429. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  430. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  431. switch (srds_s1) {
  432. #if defined(CONFIG_TARGET_T2080QDS)
  433. case 0x51:
  434. case 0x5f:
  435. case 0x65:
  436. case 0x6b:
  437. case 0x71:
  438. lane_to_slot[5] = 2;
  439. lane_to_slot[6] = 2;
  440. lane_to_slot[7] = 2;
  441. break;
  442. case 0xa6:
  443. case 0x8e:
  444. case 0x8f:
  445. case 0x82:
  446. case 0x83:
  447. case 0xd3:
  448. case 0xd9:
  449. case 0xcb:
  450. lane_to_slot[6] = 2;
  451. lane_to_slot[7] = 2;
  452. break;
  453. case 0xda:
  454. lane_to_slot[4] = 3;
  455. lane_to_slot[5] = 3;
  456. lane_to_slot[6] = 3;
  457. lane_to_slot[7] = 3;
  458. break;
  459. #elif defined(CONFIG_TARGET_T2081QDS)
  460. case 0x6b:
  461. lane_to_slot[4] = 1;
  462. lane_to_slot[5] = 3;
  463. lane_to_slot[6] = 3;
  464. lane_to_slot[7] = 3;
  465. break;
  466. case 0xca:
  467. case 0xcb:
  468. lane_to_slot[1] = 7;
  469. lane_to_slot[2] = 6;
  470. lane_to_slot[3] = 5;
  471. lane_to_slot[5] = 3;
  472. lane_to_slot[6] = 3;
  473. lane_to_slot[7] = 3;
  474. break;
  475. case 0xf2:
  476. lane_to_slot[1] = 7;
  477. lane_to_slot[2] = 7;
  478. lane_to_slot[3] = 7;
  479. lane_to_slot[5] = 4;
  480. lane_to_slot[6] = 3;
  481. lane_to_slot[7] = 7;
  482. break;
  483. #endif
  484. default:
  485. break;
  486. }
  487. }
  488. int board_eth_init(struct bd_info *bis)
  489. {
  490. #if defined(CONFIG_FMAN_ENET)
  491. int i, idx, lane, slot, interface;
  492. struct memac_mdio_info dtsec_mdio_info;
  493. struct memac_mdio_info tgec_mdio_info;
  494. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  495. u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  496. u32 srds_s1;
  497. srds_s1 = in_be32(&gur->rcwsr[4]) &
  498. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  499. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  500. initialize_lane_to_slot();
  501. /* Initialize the mdio_mux array so we can recognize empty elements */
  502. for (i = 0; i < NUM_FM_PORTS; i++)
  503. mdio_mux[i] = EMI_NONE;
  504. dtsec_mdio_info.regs =
  505. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  506. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  507. /* Register the 1G MDIO bus */
  508. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  509. tgec_mdio_info.regs =
  510. (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  511. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  512. /* Register the 10G MDIO bus */
  513. fm_memac_mdio_init(bis, &tgec_mdio_info);
  514. /* Register the muxing front-ends to the MDIO buses */
  515. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
  516. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
  517. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  518. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
  519. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  520. #if defined(CONFIG_TARGET_T2080QDS)
  521. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  522. #endif
  523. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
  524. #if defined(CONFIG_TARGET_T2081QDS)
  525. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
  526. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
  527. #endif
  528. t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
  529. /* Set the two on-board RGMII PHY address */
  530. fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
  531. if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  532. FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
  533. fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
  534. else
  535. fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
  536. switch (srds_s1) {
  537. case 0x1b:
  538. case 0x1c:
  539. case 0x95:
  540. case 0xa2:
  541. case 0x94:
  542. /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
  543. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  544. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  545. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  546. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  547. /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
  548. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  549. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  550. break;
  551. case 0x50:
  552. case 0x51:
  553. case 0x5e:
  554. case 0x5f:
  555. case 0x64:
  556. case 0x65:
  557. /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
  558. fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  559. /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
  560. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  561. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  562. break;
  563. case 0x66:
  564. case 0x67:
  565. /*
  566. * XFI does not need a PHY to work, but to avoid U-Boot use
  567. * default PHY address which is zero to a MAC when it found
  568. * a MAC has no PHY address, we give a PHY address to XFI
  569. * MAC, and should not use a real XAUI PHY address, since
  570. * MDIO can access it successfully, and then MDIO thinks
  571. * the XAUI card is used for the XFI MAC, which will cause
  572. * error.
  573. */
  574. fm_info_set_phy_address(FM1_10GEC1, 4);
  575. fm_info_set_phy_address(FM1_10GEC2, 5);
  576. fm_info_set_phy_address(FM1_10GEC3, 6);
  577. fm_info_set_phy_address(FM1_10GEC4, 7);
  578. break;
  579. case 0x6a:
  580. case 0x6b:
  581. fm_info_set_phy_address(FM1_10GEC1, 4);
  582. fm_info_set_phy_address(FM1_10GEC2, 5);
  583. fm_info_set_phy_address(FM1_10GEC3, 6);
  584. fm_info_set_phy_address(FM1_10GEC4, 7);
  585. /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
  586. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  587. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  588. break;
  589. case 0x6c:
  590. case 0x6d:
  591. fm_info_set_phy_address(FM1_10GEC1, 4);
  592. fm_info_set_phy_address(FM1_10GEC2, 5);
  593. /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
  594. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  595. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  596. break;
  597. case 0x70:
  598. case 0x71:
  599. /* SGMII in Slot3 */
  600. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  601. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  602. /* SGMII in Slot2 */
  603. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  604. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  605. break;
  606. case 0xa6:
  607. case 0x8e:
  608. case 0x8f:
  609. case 0x82:
  610. case 0x83:
  611. /* SGMII in Slot3 */
  612. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  613. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  614. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  615. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  616. /* SGMII in Slot2 */
  617. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  618. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  619. break;
  620. case 0xa4:
  621. case 0x96:
  622. case 0x8a:
  623. /* SGMII in Slot3 */
  624. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  625. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  626. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  627. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  628. break;
  629. #if defined(CONFIG_TARGET_T2080QDS)
  630. case 0xd9:
  631. case 0xd3:
  632. case 0xcb:
  633. /* SGMII in Slot3 */
  634. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  635. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  636. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  637. /* SGMII in Slot2 */
  638. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  639. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  640. break;
  641. #elif defined(CONFIG_TARGET_T2081QDS)
  642. case 0xca:
  643. case 0xcb:
  644. /* SGMII in Slot3 */
  645. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
  646. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  647. /* SGMII in Slot5 */
  648. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  649. /* SGMII in Slot6 */
  650. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  651. /* SGMII in Slot7 */
  652. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
  653. break;
  654. #endif
  655. case 0xf2:
  656. /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
  657. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  658. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
  659. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
  660. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  661. break;
  662. default:
  663. break;
  664. }
  665. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  666. idx = i - FM1_DTSEC1;
  667. interface = fm_info_get_enet_if(i);
  668. switch (interface) {
  669. case PHY_INTERFACE_MODE_SGMII:
  670. lane = serdes_get_first_lane(FSL_SRDS_1,
  671. SGMII_FM1_DTSEC1 + idx);
  672. if (lane < 0)
  673. break;
  674. slot = lane_to_slot[lane];
  675. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  676. idx + 1, slot);
  677. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  678. fm_disable_port(i);
  679. switch (slot) {
  680. case 1:
  681. mdio_mux[i] = EMI1_SLOT1;
  682. fm_info_set_mdio(i, mii_dev_for_muxval(
  683. mdio_mux[i]));
  684. break;
  685. case 2:
  686. mdio_mux[i] = EMI1_SLOT2;
  687. fm_info_set_mdio(i, mii_dev_for_muxval(
  688. mdio_mux[i]));
  689. break;
  690. case 3:
  691. mdio_mux[i] = EMI1_SLOT3;
  692. fm_info_set_mdio(i, mii_dev_for_muxval(
  693. mdio_mux[i]));
  694. break;
  695. #if defined(CONFIG_TARGET_T2081QDS)
  696. case 5:
  697. mdio_mux[i] = EMI1_SLOT5;
  698. fm_info_set_mdio(i, mii_dev_for_muxval(
  699. mdio_mux[i]));
  700. break;
  701. case 6:
  702. mdio_mux[i] = EMI1_SLOT6;
  703. fm_info_set_mdio(i, mii_dev_for_muxval(
  704. mdio_mux[i]));
  705. break;
  706. case 7:
  707. mdio_mux[i] = EMI1_SLOT7;
  708. fm_info_set_mdio(i, mii_dev_for_muxval(
  709. mdio_mux[i]));
  710. break;
  711. #endif
  712. }
  713. break;
  714. case PHY_INTERFACE_MODE_RGMII:
  715. if (i == FM1_DTSEC3)
  716. mdio_mux[i] = EMI1_RGMII1;
  717. else if (i == FM1_DTSEC4 || FM1_DTSEC10)
  718. mdio_mux[i] = EMI1_RGMII2;
  719. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  720. break;
  721. default:
  722. break;
  723. }
  724. }
  725. for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  726. idx = i - FM1_10GEC1;
  727. switch (fm_info_get_enet_if(i)) {
  728. case PHY_INTERFACE_MODE_XGMII:
  729. if (srds_s1 == 0x51) {
  730. lane = serdes_get_first_lane(FSL_SRDS_1,
  731. XAUI_FM1_MAC9 + idx);
  732. } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
  733. lane = serdes_get_first_lane(FSL_SRDS_1,
  734. HIGIG_FM1_MAC9 + idx);
  735. } else {
  736. if (i == FM1_10GEC1 || i == FM1_10GEC2)
  737. lane = serdes_get_first_lane(FSL_SRDS_1,
  738. XFI_FM1_MAC9 + idx);
  739. else
  740. lane = serdes_get_first_lane(FSL_SRDS_1,
  741. XFI_FM1_MAC1 + idx);
  742. }
  743. if (lane < 0)
  744. break;
  745. mdio_mux[i] = EMI2;
  746. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  747. if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
  748. (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
  749. (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
  750. (srds_s1 == 0x71)) {
  751. /* As XFI is in cage intead of a slot, so
  752. * ensure doesn't disable the corresponding port
  753. */
  754. break;
  755. }
  756. slot = lane_to_slot[lane];
  757. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  758. fm_disable_port(i);
  759. break;
  760. default:
  761. break;
  762. }
  763. }
  764. cpu_eth_init(bis);
  765. #endif /* CONFIG_FMAN_ENET */
  766. return pci_eth_init(bis);
  767. }