ddr.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <hwconfig.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/mmu.h>
  11. #include <fsl_ddr_sdram.h>
  12. #include <fsl_ddr_dimm_params.h>
  13. #include <asm/fsl_law.h>
  14. #include "ddr.h"
  15. DECLARE_GLOBAL_DATA_PTR;
  16. void fsl_ddr_board_options(memctl_options_t *popts,
  17. dimm_params_t *pdimm,
  18. unsigned int ctrl_num)
  19. {
  20. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  21. ulong ddr_freq;
  22. if (ctrl_num > 1) {
  23. printf("Not supported controller number %d\n", ctrl_num);
  24. return;
  25. }
  26. if (!pdimm->n_ranks)
  27. return;
  28. /*
  29. * we use identical timing for all slots. If needed, change the code
  30. * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  31. */
  32. if (popts->registered_dimm_en)
  33. pbsp = rdimms[0];
  34. else
  35. pbsp = udimms[0];
  36. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  37. * freqency and n_banks specified in board_specific_parameters table.
  38. */
  39. ddr_freq = get_ddr_freq(0) / 1000000;
  40. while (pbsp->datarate_mhz_high) {
  41. if (pbsp->n_ranks == pdimm->n_ranks &&
  42. (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  43. if (ddr_freq <= pbsp->datarate_mhz_high) {
  44. popts->clk_adjust = pbsp->clk_adjust;
  45. popts->wrlvl_start = pbsp->wrlvl_start;
  46. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  47. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  48. goto found;
  49. }
  50. pbsp_highest = pbsp;
  51. }
  52. pbsp++;
  53. }
  54. if (pbsp_highest) {
  55. printf("Error: board specific timing not found");
  56. printf("for data rate %lu MT/s\n", ddr_freq);
  57. printf("Trying to use the highest speed (%u) parameters\n",
  58. pbsp_highest->datarate_mhz_high);
  59. popts->clk_adjust = pbsp_highest->clk_adjust;
  60. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  61. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  62. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  63. } else {
  64. panic("DIMM is not supported by this board");
  65. }
  66. found:
  67. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  68. "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  69. "wrlvl_ctrl_3 0x%x\n",
  70. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  71. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  72. pbsp->wrlvl_ctl_3);
  73. /*
  74. * Factors to consider for half-strength driver enable:
  75. * - number of DIMMs installed
  76. */
  77. popts->half_strength_driver_enable = 0;
  78. /*
  79. * Write leveling override
  80. */
  81. popts->wrlvl_override = 1;
  82. popts->wrlvl_sample = 0xf;
  83. /*
  84. * Rtt and Rtt_WR override
  85. */
  86. popts->rtt_override = 0;
  87. /* Enable ZQ calibration */
  88. popts->zq_en = 1;
  89. /* DHC_EN =1, ODT = 75 Ohm */
  90. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  91. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  92. /* optimize cpo for erratum A-009942 */
  93. popts->cpo_sample = 0x64;
  94. }
  95. int dram_init(void)
  96. {
  97. phys_size_t dram_size;
  98. #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
  99. puts("Initializing....using SPD\n");
  100. dram_size = fsl_ddr_sdram();
  101. #else
  102. /* DDR has been initialised by first stage boot loader */
  103. dram_size = fsl_ddr_sdram_size();
  104. #endif
  105. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  106. dram_size *= 0x100000;
  107. gd->ram_size = dram_size;
  108. return 0;
  109. }