README 11 KB

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  1. The T2080QDS is a high-performance computing evaluation, development and
  2. test platform supporting the T2080 QorIQ Power Architecture processor.
  3. T2080 SoC Overview
  4. ------------------
  5. The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
  6. Architecture processor cores with high-performance datapath acceleration
  7. logic and network and peripheral bus interfaces required for networking,
  8. telecom/datacom, wireless infrastructure, and mil/aerospace applications.
  9. T2080 includes the following functions and features:
  10. - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
  11. - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
  12. - Hierarchical interconnect fabric
  13. - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
  14. - Data Path Acceleration Architecture (DPAA) incorporating acceleration
  15. - 16 SerDes lanes up to 10.3125 GHz
  16. - 8 Ethernet interfaces, supporting combinations of the following:
  17. - Up to four 10 Gbps Ethernet MACs
  18. - Up to eight 1 Gbps Ethernet MACs
  19. - Up to four 2.5 Gbps Ethernet MACs
  20. - High-speed peripheral interfaces
  21. - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
  22. - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
  23. - Additional peripheral interfaces
  24. - Two serial ATA (SATA 2.0) controllers
  25. - Two high-speed USB 2.0 controllers with integrated PHY
  26. - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
  27. - Enhanced serial peripheral interface (eSPI)
  28. - Four I2C controllers
  29. - Four 2-pin UARTs or two 4-pin UARTs
  30. - Integrated Flash Controller supporting NAND and NOR flash
  31. - Three eight-channel DMA engines
  32. - Support for hardware virtualization and partitioning enforcement
  33. - QorIQ Platform's Trust Architecture 2.0
  34. Differences between T2080 and T2081
  35. -----------------------------------
  36. Feature T2080 T2081
  37. 1G Ethernet numbers: 8 6
  38. 10G Ethernet numbers: 4 2
  39. SerDes lanes: 16 8
  40. Serial RapidIO,RMan: 2 no
  41. SATA Controller: 2 no
  42. Aurora: yes no
  43. SoC Package: 896-pins 780-pins
  44. T2080QDS feature overview
  45. -------------------------
  46. Processor:
  47. - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
  48. Memory:
  49. - Single memory controller capable of supporting DDR3 and DDR3-LV devices
  50. - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
  51. Ethernet interfaces:
  52. - Two 1Gbps RGMII on-board ports
  53. - Four 10Gbps XFI on-board cages
  54. - 1Gbps/2.5Gbps SGMII Riser card
  55. - 10Gbps XAUI Riser card
  56. Accelerator:
  57. - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
  58. SerDes:
  59. - 16 lanes up to 10.3125GHz
  60. - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
  61. IFC:
  62. - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
  63. eSPI:
  64. - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
  65. USB:
  66. - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
  67. PCIE:
  68. - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
  69. SATA:
  70. - Two SATA 2.0 ports on-board
  71. SRIO:
  72. - Two Serial RapidIO 2.0 ports up to 5 GHz
  73. eSDHC:
  74. - Supports SD/SDHC/SDXC/eMMC Card
  75. I2C:
  76. - Four I2C controllers.
  77. UART:
  78. - Dual 4-pins UART serial ports
  79. System Logic:
  80. - QIXIS-II FPGA system controll
  81. Debug Features:
  82. - Support Legacy, COP/JTAG, Aurora, Event and EVT
  83. XFI:
  84. - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
  85. a on-board SFP+ cages, which to house optical module (fiber cable) or
  86. direct attach cable(copper), the copper cable is used to emulate
  87. 10GBASE-KR scenario.
  88. So, for XFI usage, there are two scenarios, one will use fiber cable,
  89. another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
  90. introduced to indicate a XFI port will use copper cable, and U-Boot
  91. will fixup the dtb accordingly.
  92. It's used as: fsl_10gkr_copper:<10g_mac_name>
  93. The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
  94. do not have to be coexist in hwconfig. If a MAC is listed in the env
  95. "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
  96. will be used by default.
  97. for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
  98. hwconfig, then both four XFI ports will use copper cable.
  99. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
  100. XFI ports will use copper cable, the other two XFI ports will use fiber
  101. cable.
  102. 1000BASE-KX(1G-KX):
  103. - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
  104. runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
  105. in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
  106. Register 1 (PCCR1), and U-Boot fixup the dtb for kernel to do proper
  107. initialization.
  108. Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
  109. 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
  110. MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
  111. stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
  112. For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
  113. hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
  114. System Memory map
  115. ----------------
  116. Start Address End Address Description Size
  117. 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
  118. 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
  119. 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
  120. 0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
  121. 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
  122. 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
  123. 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
  124. 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
  125. 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
  126. 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
  127. 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
  128. 0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
  129. 0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
  130. 0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
  131. 0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
  132. 0x0_0000_0000 0x0_ffff_ffff DDR 4GB
  133. 128M NOR Flash memory Map
  134. -------------------------
  135. Start Address End Address Definition Max size
  136. 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
  137. 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
  138. 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
  139. 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
  140. 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
  141. 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
  142. 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
  143. 0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
  144. 0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
  145. 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
  146. 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
  147. 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
  148. 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
  149. 0xE8000000 0xE801FFFF RCW (current bank) 128KB
  150. Software configurations and board settings
  151. ------------------------------------------
  152. 1. NOR boot:
  153. a. build NOR boot image
  154. $ make T2080QDS_config
  155. $ make
  156. b. program u-boot.bin image to NOR flash
  157. => tftp 1000000 u-boot.bin
  158. => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
  159. set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
  160. Switching between default bank0 and alternate bank4 on NOR flash
  161. To change boot source to vbank4:
  162. by software: run command 'qixis_reset altbank' in U-Boot.
  163. by DIP-switch: set SW6[1:4] = '0100'
  164. To change boot source to vbank0:
  165. by software: run command 'qixis_reset' in U-Boot.
  166. by DIP-Switch: set SW6[1:4] = '0000'
  167. 2. NAND Boot:
  168. a. build PBL image for NAND boot
  169. $ make T2080QDS_NAND_config
  170. $ make
  171. b. program u-boot-with-spl-pbl.bin to NAND flash
  172. => tftp 1000000 u-boot-with-spl-pbl.bin
  173. => nand erase 0 $filesize
  174. => nand write 1000000 0 $filesize
  175. set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
  176. 3. SPI Boot:
  177. a. build PBL image for SPI boot
  178. $ make T2080QDS_SPIFLASH_config
  179. $ make
  180. b. program u-boot-with-spl-pbl.bin to SPI flash
  181. => tftp 1000000 u-boot-with-spl-pbl.bin
  182. => sf probe 0
  183. => sf erase 0 f0000
  184. => sf write 1000000 0 $filesize
  185. set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
  186. 4. SD Boot:
  187. a. build PBL image for SD boot
  188. $ make T2080QDS_SDCARD_config
  189. $ make
  190. b. program u-boot-with-spl-pbl.bin to SD/MMC card
  191. => tftp 1000000 u-boot-with-spl-pbl.bin
  192. => mmc write 1000000 8 0x800
  193. => tftp 1000000 fsl_fman_ucode_T2080_xx.bin
  194. => mmc write 1000000 0x820 80
  195. set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
  196. 2-stage NAND/SPI/SD boot loader
  197. -------------------------------
  198. PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
  199. SPL further initializes DDR using SPD and environment variables
  200. and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
  201. Finally SPL transers control to U-Boot for futher booting.
  202. SPL has following features:
  203. - Executes within 256K
  204. - No relocation required
  205. Run time view of SPL framework
  206. -------------------------------------------------
  207. |Area | Address |
  208. -------------------------------------------------
  209. |SecureBoot header | 0xFFFC0000 (32KB) |
  210. -------------------------------------------------
  211. |GD, BD | 0xFFFC8000 (4KB) |
  212. -------------------------------------------------
  213. |ENV | 0xFFFC9000 (8KB) |
  214. -------------------------------------------------
  215. |HEAP | 0xFFFCB000 (50KB) |
  216. -------------------------------------------------
  217. |STACK | 0xFFFD8000 (22KB) |
  218. -------------------------------------------------
  219. |U-Boot SPL | 0xFFFD8000 (160KB) |
  220. -------------------------------------------------
  221. NAND Flash memory Map on T2080QDS
  222. --------------------------------------------------------------
  223. Start End Definition Size
  224. 0x000000 0x0FFFFF U-Boot img 1MB (2 blocks)
  225. 0x100000 0x17FFFF U-Boot env 512KB (1 block)
  226. 0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
  227. Micro SD Card memory Map on T2080QDS
  228. ----------------------------------------------------
  229. Block #blocks Definition Size
  230. 0x008 2048 U-Boot img 1MB
  231. 0x800 0016 U-Boot env 8KB
  232. 0x820 0128 FMAN ucode 64KB
  233. SPI Flash memory Map on T2080QDS
  234. ----------------------------------------------------
  235. Start End Definition Size
  236. 0x000000 0x0FFFFF U-Boot img 1MB
  237. 0x100000 0x101FFF U-Boot env 8KB
  238. 0x110000 0x11FFFF FMAN ucode 64KB
  239. How to update the ucode of Freescale FMAN
  240. -----------------------------------------
  241. => tftp 1000000 fsl_fman_ucode_t2080_xx.bin
  242. => pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
  243. For more details, please refer to T2080QDS User Guide and access
  244. website www.freescale.com and Freescale QorIQ SDK Infocenter document.
  245. Device tree support and how to enable it for different configs
  246. --------------------------------------------------------------
  247. Device tree support is available for t2080qds for below mentioned boot,
  248. 1. NOR Boot
  249. 2. NAND Boot
  250. 3. SD Boot
  251. 4. SPIFLASH Boot
  252. To enable device tree support for other boot, below configs need to be
  253. enabled in relative defconfig file,
  254. 1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required)
  255. 2. CONFIG_OF_CONTROL
  256. 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
  257. CONFIG_RESET_VECTOR_ADDRESS - 0xffc
  258. If device tree support is enabled in defconfig,
  259. 1. use 'u-boot-with-dtb.bin' for NOR boot.
  260. 2. use 'u-boot-with-spl-pbl.bin' for other boot.