s32v234evb.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/siul.h>
  10. #include <asm/arch/lpddr2.h>
  11. #include <asm/arch/clock.h>
  12. #include <mmc.h>
  13. #include <fsl_esdhc_imx.h>
  14. #include <miiphy.h>
  15. #include <netdev.h>
  16. #include <i2c.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. void setup_iomux_ddr(void)
  19. {
  20. lpddr2_config_iomux(DDR0);
  21. lpddr2_config_iomux(DDR1);
  22. }
  23. void ddr_phy_init(void)
  24. {
  25. }
  26. void ddr_ctrl_init(void)
  27. {
  28. config_mmdc(0);
  29. config_mmdc(1);
  30. }
  31. int dram_init(void)
  32. {
  33. setup_iomux_ddr();
  34. ddr_ctrl_init();
  35. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  36. return 0;
  37. }
  38. static void setup_iomux_uart(void)
  39. {
  40. /* Muxing for linflex */
  41. /* Replace the magic values after bringup */
  42. /* set TXD - MSCR[12] PA12 */
  43. writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD));
  44. /* set RXD - MSCR[11] - PA11 */
  45. writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD));
  46. /* set RXD - IMCR[200] - 200 */
  47. writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD));
  48. }
  49. static void setup_iomux_enet(void)
  50. {
  51. }
  52. static void setup_iomux_i2c(void)
  53. {
  54. }
  55. #ifdef CONFIG_SYS_USE_NAND
  56. void setup_iomux_nfc(void)
  57. {
  58. }
  59. #endif
  60. #ifdef CONFIG_FSL_ESDHC_IMX
  61. struct fsl_esdhc_cfg esdhc_cfg[1] = {
  62. {USDHC_BASE_ADDR},
  63. };
  64. int board_mmc_getcd(struct mmc *mmc)
  65. {
  66. /* eSDHC1 is always present */
  67. return 1;
  68. }
  69. int board_mmc_init(struct bd_info * bis)
  70. {
  71. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
  72. /* Set iomux PADS for USDHC */
  73. /* PK6 pad: uSDHC clk */
  74. writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150));
  75. writel(0x3, SIUL2_MSCRn(902));
  76. /* PK7 pad: uSDHC CMD */
  77. writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151));
  78. writel(0x3, SIUL2_MSCRn(901));
  79. /* PK8 pad: uSDHC DAT0 */
  80. writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152));
  81. writel(0x3, SIUL2_MSCRn(903));
  82. /* PK9 pad: uSDHC DAT1 */
  83. writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153));
  84. writel(0x3, SIUL2_MSCRn(904));
  85. /* PK10 pad: uSDHC DAT2 */
  86. writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154));
  87. writel(0x3, SIUL2_MSCRn(905));
  88. /* PK11 pad: uSDHC DAT3 */
  89. writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155));
  90. writel(0x3, SIUL2_MSCRn(906));
  91. /* PK15 pad: uSDHC DAT4 */
  92. writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159));
  93. writel(0x3, SIUL2_MSCRn(907));
  94. /* PL0 pad: uSDHC DAT5 */
  95. writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160));
  96. writel(0x3, SIUL2_MSCRn(908));
  97. /* PL1 pad: uSDHC DAT6 */
  98. writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161));
  99. writel(0x3, SIUL2_MSCRn(909));
  100. /* PL2 pad: uSDHC DAT7 */
  101. writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162));
  102. writel(0x3, SIUL2_MSCRn(910));
  103. return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
  104. }
  105. #endif
  106. static void mscm_init(void)
  107. {
  108. struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
  109. int i;
  110. for (i = 0; i < MSCM_IRSPRC_NUM; i++)
  111. writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]);
  112. }
  113. int board_phy_config(struct phy_device *phydev)
  114. {
  115. if (phydev->drv->config)
  116. phydev->drv->config(phydev);
  117. return 0;
  118. }
  119. int board_early_init_f(void)
  120. {
  121. clock_init();
  122. mscm_init();
  123. setup_iomux_uart();
  124. setup_iomux_enet();
  125. setup_iomux_i2c();
  126. #ifdef CONFIG_SYS_USE_NAND
  127. setup_iomux_nfc();
  128. #endif
  129. return 0;
  130. }
  131. int board_init(void)
  132. {
  133. /* address of boot parameters */
  134. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  135. return 0;
  136. }
  137. int checkboard(void)
  138. {
  139. puts("Board: s32v234evb\n");
  140. return 0;
  141. }