p2041rdb.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011,2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <fdt_support.h>
  9. #include <image.h>
  10. #include <init.h>
  11. #include <netdev.h>
  12. #include <linux/compiler.h>
  13. #include <asm/mmu.h>
  14. #include <asm/processor.h>
  15. #include <asm/cache.h>
  16. #include <asm/immap_85xx.h>
  17. #include <asm/fsl_law.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_liodn.h>
  20. #include <fm_eth.h>
  21. extern void pci_of_setup(void *blob, struct bd_info *bd);
  22. #include "cpld.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int checkboard(void)
  25. {
  26. u8 sw;
  27. struct cpu_type *cpu = gd->arch.cpu;
  28. unsigned int i;
  29. printf("Board: %sRDB, ", cpu->name);
  30. printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
  31. CPLD_READ(cpld_ver_sub));
  32. sw = CPLD_READ(fbank_sel);
  33. printf("vBank: %d\n", sw & 0x1);
  34. /*
  35. * Display the actual SERDES reference clocks as configured by the
  36. * dip switches on the board. Note that the SWx registers could
  37. * technically be set to force the reference clocks to match the
  38. * values that the SERDES expects (or vice versa). For now, however,
  39. * we just display both values and hope the user notices when they
  40. * don't match.
  41. */
  42. puts("SERDES Reference Clocks: ");
  43. sw = in_8(&CPLD_SW(2)) >> 2;
  44. for (i = 0; i < 2; i++) {
  45. static const char * const freq[][3] = {{"0", "100", "125"},
  46. {"100", "156.25", "125"}
  47. };
  48. unsigned int clock = (sw >> (2 * i)) & 3;
  49. printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
  50. }
  51. puts("\n");
  52. return 0;
  53. }
  54. int board_early_init_f(void)
  55. {
  56. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  57. /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
  58. setbits_be32(&gur->ddrclkdr, 0x000f000f);
  59. return 0;
  60. }
  61. #define CPLD_LANE_A_SEL 0x1
  62. #define CPLD_LANE_G_SEL 0x2
  63. #define CPLD_LANE_C_SEL 0x4
  64. #define CPLD_LANE_D_SEL 0x8
  65. void board_config_lanes_mux(void)
  66. {
  67. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  68. int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
  69. FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
  70. u8 mux = 0;
  71. switch (srds_prtcl) {
  72. case 0x2:
  73. case 0x5:
  74. case 0x9:
  75. case 0xa:
  76. case 0xf:
  77. break;
  78. case 0x8:
  79. mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
  80. break;
  81. case 0x14:
  82. mux |= CPLD_LANE_A_SEL;
  83. break;
  84. case 0x17:
  85. mux |= CPLD_LANE_G_SEL;
  86. break;
  87. case 0x16:
  88. case 0x19:
  89. case 0x1a:
  90. mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
  91. break;
  92. case 0x1c:
  93. mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
  94. break;
  95. default:
  96. printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
  97. break;
  98. }
  99. CPLD_WRITE(serdes_mux, mux);
  100. }
  101. int board_early_init_r(void)
  102. {
  103. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  104. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  105. /*
  106. * Remap Boot flash + PROMJET region to caching-inhibited
  107. * so that flash can be erased properly.
  108. */
  109. /* Flush d-cache and invalidate i-cache of any FLASH data */
  110. flush_dcache();
  111. invalidate_icache();
  112. if (flash_esel == -1) {
  113. /* very unlikely unless something is messed up */
  114. puts("Error: Could not find TLB for FLASH BASE\n");
  115. flash_esel = 2; /* give our best effort to continue */
  116. } else {
  117. /* invalidate existing TLB entry for flash + promjet */
  118. disable_tlb(flash_esel);
  119. }
  120. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  121. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  122. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  123. board_config_lanes_mux();
  124. return 0;
  125. }
  126. unsigned long get_board_sys_clk(unsigned long dummy)
  127. {
  128. u8 sysclk_conf = CPLD_READ(sysclk_sw1);
  129. switch (sysclk_conf & 0x7) {
  130. case CPLD_SYSCLK_83:
  131. return 83333333;
  132. case CPLD_SYSCLK_100:
  133. return 100000000;
  134. default:
  135. return 66666666;
  136. }
  137. }
  138. #define NUM_SRDS_BANKS 2
  139. int misc_init_r(void)
  140. {
  141. serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  142. u32 actual[NUM_SRDS_BANKS];
  143. unsigned int i;
  144. u8 sw;
  145. static const int freq[][3] = {
  146. {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
  147. {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
  148. SRDS_PLLCR0_RFCK_SEL_125}
  149. };
  150. sw = in_8(&CPLD_SW(2)) >> 2;
  151. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  152. unsigned int clock = (sw >> (2 * i)) & 3;
  153. if (clock == 0x3) {
  154. printf("Warning: SDREFCLK%u switch setting of '11' is "
  155. "unsupported\n", i + 1);
  156. break;
  157. }
  158. if (i == 0 && clock == 0)
  159. puts("Warning: SDREFCLK1 switch setting of"
  160. "'00' is unsupported\n");
  161. else
  162. actual[i] = freq[i][clock];
  163. /*
  164. * PC board uses a different CPLD with PB board, this CPLD
  165. * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
  166. * board has cpld_ver_sub = 0, and pcba_ver = 4.
  167. */
  168. if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
  169. (CPLD_READ(pcba_ver) == 5)) {
  170. /* PC board bank2 frequency */
  171. actual[i] = freq[i-1][clock];
  172. }
  173. }
  174. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  175. u32 expected = in_be32(&regs->bank[i].pllcr0);
  176. expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
  177. if (expected != actual[i]) {
  178. printf("Warning: SERDES bank %u expects reference clock"
  179. " %sMHz, but actual is %sMHz\n", i + 1,
  180. serdes_clock_to_string(expected),
  181. serdes_clock_to_string(actual[i]));
  182. }
  183. }
  184. return 0;
  185. }
  186. int ft_board_setup(void *blob, struct bd_info *bd)
  187. {
  188. phys_addr_t base;
  189. phys_size_t size;
  190. ft_cpu_setup(blob, bd);
  191. base = env_get_bootm_low();
  192. size = env_get_bootm_size();
  193. fdt_fixup_memory(blob, (u64)base, (u64)size);
  194. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  195. fsl_fdt_fixup_dr_usb(blob, bd);
  196. #endif
  197. #ifdef CONFIG_PCI
  198. pci_of_setup(blob, bd);
  199. #endif
  200. fdt_fixup_liodn(blob);
  201. #ifdef CONFIG_SYS_DPAA_FMAN
  202. #ifndef CONFIG_DM_ETH
  203. fdt_fixup_fman_ethernet(blob);
  204. #endif
  205. #endif
  206. return 0;
  207. }