ddr.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <hwconfig.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/mmu.h>
  11. #include <fsl_ddr_sdram.h>
  12. #include <fsl_ddr_dimm_params.h>
  13. #include <asm/fsl_law.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. struct board_specific_parameters {
  16. u32 n_ranks;
  17. u32 datarate_mhz_high;
  18. u32 clk_adjust;
  19. u32 wrlvl_start;
  20. u32 cpo;
  21. u32 write_data_delay;
  22. u32 force_2t;
  23. };
  24. /*
  25. * This table contains all valid speeds we want to override with board
  26. * specific parameters. datarate_mhz_high values need to be in ascending order
  27. * for each n_ranks group.
  28. *
  29. * ranges for parameters:
  30. * wr_data_delay = 0-6
  31. * clk adjust = 0-8
  32. * cpo 2-0x1E (30)
  33. */
  34. static const struct board_specific_parameters dimm0[] = {
  35. /*
  36. * memory controller 0
  37. * num| hi| clk| wrlvl | cpo |wrdata|2T
  38. * ranks| mhz|adjst| start | delay|
  39. */
  40. {2, 750, 3, 5, 0xff, 2, 0},
  41. {2, 1250, 4, 6, 0xff, 2, 0},
  42. {2, 1350, 5, 7, 0xff, 2, 0},
  43. {2, 1666, 5, 8, 0xff, 2, 0},
  44. {}
  45. };
  46. void fsl_ddr_board_options(memctl_options_t *popts,
  47. dimm_params_t *pdimm,
  48. unsigned int ctrl_num)
  49. {
  50. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  51. ulong ddr_freq;
  52. if (ctrl_num) {
  53. printf("Wrong parameter for controller number %d", ctrl_num);
  54. return;
  55. }
  56. if (!pdimm->n_ranks)
  57. return;
  58. pbsp = dimm0;
  59. /*
  60. * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  61. * freqency and n_banks specified in board_specific_parameters table.
  62. */
  63. ddr_freq = get_ddr_freq(0) / 1000000;
  64. while (pbsp->datarate_mhz_high) {
  65. if (pbsp->n_ranks == pdimm->n_ranks) {
  66. if (ddr_freq <= pbsp->datarate_mhz_high) {
  67. popts->cpo_override = pbsp->cpo;
  68. popts->write_data_delay =
  69. pbsp->write_data_delay;
  70. popts->clk_adjust = pbsp->clk_adjust;
  71. popts->wrlvl_start = pbsp->wrlvl_start;
  72. popts->twot_en = pbsp->force_2t;
  73. goto found;
  74. }
  75. pbsp_highest = pbsp;
  76. }
  77. pbsp++;
  78. }
  79. if (pbsp_highest) {
  80. printf("Error: board specific timing not found "
  81. "for data rate %lu MT/s!\n"
  82. "Trying to use the highest speed (%u) parameters\n",
  83. ddr_freq, pbsp_highest->datarate_mhz_high);
  84. popts->cpo_override = pbsp_highest->cpo;
  85. popts->write_data_delay = pbsp_highest->write_data_delay;
  86. popts->clk_adjust = pbsp_highest->clk_adjust;
  87. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  88. popts->twot_en = pbsp_highest->force_2t;
  89. } else {
  90. panic("DIMM is not supported by this board");
  91. }
  92. found:
  93. /*
  94. * Factors to consider for half-strength driver enable:
  95. * - number of DIMMs installed
  96. */
  97. popts->half_strength_driver_enable = 0;
  98. /* Write leveling override */
  99. popts->wrlvl_override = 1;
  100. popts->wrlvl_sample = 0xf;
  101. /* Rtt and Rtt_WR override */
  102. popts->rtt_override = 0;
  103. /* Enable ZQ calibration */
  104. popts->zq_en = 1;
  105. /* DHC_EN =1, ODT = 60 Ohm */
  106. popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
  107. }
  108. int dram_init(void)
  109. {
  110. phys_size_t dram_size = 0;
  111. puts("Initializing....");
  112. if (fsl_use_spd()) {
  113. puts("using SPD\n");
  114. dram_size = fsl_ddr_sdram();
  115. } else {
  116. puts("no SPD and fixed parameters\n");
  117. return -ENXIO;
  118. }
  119. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  120. dram_size *= 0x100000;
  121. debug(" DDR: ");
  122. gd->ram_size = dram_size;
  123. return 0;
  124. }