cpld.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * Copyright 2011 Freescale Semiconductor
  4. * Author: Mingkai Hu <Mingkai.hu@freescale.com>
  5. *
  6. * This file provides support for the board-specific CPLD used on some Freescale
  7. * reference boards.
  8. *
  9. * The following macros need to be defined:
  10. *
  11. * CPLD_BASE - The virtual address of the base of the CPLD register map
  12. */
  13. #include <common.h>
  14. #include <command.h>
  15. #include <asm/io.h>
  16. #include "cpld.h"
  17. static u8 __cpld_read(unsigned int reg)
  18. {
  19. void *p = (void *)CPLD_BASE;
  20. return in_8(p + reg);
  21. }
  22. u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
  23. static void __cpld_write(unsigned int reg, u8 value)
  24. {
  25. void *p = (void *)CPLD_BASE;
  26. out_8(p + reg, value);
  27. }
  28. void cpld_write(unsigned int reg, u8 value)
  29. __attribute__((weak, alias("__cpld_write")));
  30. /*
  31. * Reset the board. This honors the por_cfg registers.
  32. */
  33. void __cpld_reset(void)
  34. {
  35. CPLD_WRITE(system_rst, 1);
  36. }
  37. void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
  38. /**
  39. * Set the boot bank to the alternate bank
  40. */
  41. void __cpld_set_altbank(void)
  42. {
  43. u8 reg5 = CPLD_READ(sw_ctl_on);
  44. CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
  45. CPLD_WRITE(fbank_sel, 1);
  46. CPLD_WRITE(system_rst, 1);
  47. }
  48. void cpld_set_altbank(void)
  49. __attribute__((weak, alias("__cpld_set_altbank")));
  50. /**
  51. * Set the boot bank to the default bank
  52. */
  53. void __cpld_set_defbank(void)
  54. {
  55. CPLD_WRITE(system_rst_default, 1);
  56. }
  57. void cpld_set_defbank(void)
  58. __attribute__((weak, alias("__cpld_set_defbank")));
  59. #ifdef DEBUG
  60. static void cpld_dump_regs(void)
  61. {
  62. printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
  63. printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
  64. printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver));
  65. printf("system_rst = 0x%02x\n", CPLD_READ(system_rst));
  66. printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on));
  67. printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg));
  68. printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe));
  69. printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel));
  70. printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk));
  71. printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk));
  72. printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel));
  73. printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux));
  74. printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2)));
  75. putc('\n');
  76. }
  77. #endif
  78. int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  79. {
  80. int rc = 0;
  81. if (argc <= 1)
  82. return cmd_usage(cmdtp);
  83. if (strcmp(argv[1], "reset") == 0) {
  84. if (strcmp(argv[2], "altbank") == 0)
  85. cpld_set_altbank();
  86. else
  87. cpld_set_defbank();
  88. } else if (strcmp(argv[1], "lane_mux") == 0) {
  89. u32 lane = simple_strtoul(argv[2], NULL, 16);
  90. u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
  91. u8 reg = CPLD_READ(serdes_mux);
  92. switch (lane) {
  93. case 0x6:
  94. reg &= ~SERDES_MUX_LANE_6_MASK;
  95. reg |= val << SERDES_MUX_LANE_6_SHIFT;
  96. break;
  97. case 0xa:
  98. reg &= ~SERDES_MUX_LANE_A_MASK;
  99. reg |= val << SERDES_MUX_LANE_A_SHIFT;
  100. break;
  101. case 0xc:
  102. reg &= ~SERDES_MUX_LANE_C_MASK;
  103. reg |= val << SERDES_MUX_LANE_C_SHIFT;
  104. break;
  105. case 0xd:
  106. reg &= ~SERDES_MUX_LANE_D_MASK;
  107. reg |= val << SERDES_MUX_LANE_D_SHIFT;
  108. break;
  109. default:
  110. printf("Invalid value\n");
  111. break;
  112. }
  113. CPLD_WRITE(serdes_mux, reg);
  114. #ifdef DEBUG
  115. } else if (strcmp(argv[1], "dump") == 0) {
  116. cpld_dump_regs();
  117. #endif
  118. } else
  119. rc = cmd_usage(cmdtp);
  120. return rc;
  121. }
  122. U_BOOT_CMD(
  123. cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
  124. "Reset the board or pin mulexing selection using the CPLD sequencer",
  125. "reset - hard reset to default bank\n"
  126. "cpld_cmd reset altbank - reset to alternate bank\n"
  127. "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
  128. " lane 6: 0 -> slot1\n"
  129. " 1 -> SGMII (Default)\n"
  130. " lane a: 0 -> slot2\n"
  131. " 1 -> AURORA (Default)\n"
  132. " lane c: 0 -> slot2\n"
  133. " 1 -> SATA0 (Default)\n"
  134. " lane d: 0 -> slot2\n"
  135. " 1 -> SATA1 (Default)\n"
  136. #ifdef DEBUG
  137. "cpld_cmd dump - display the CPLD registers\n"
  138. #endif
  139. );