ddr.c 6.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <vsprintf.h>
  7. #include <asm/mmu.h>
  8. #include <asm/immap_85xx.h>
  9. #include <asm/processor.h>
  10. #include <fsl_ddr_sdram.h>
  11. #include <fsl_ddr_dimm_params.h>
  12. #include <asm/io.h>
  13. #include <asm/fsl_law.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. #ifndef CONFIG_SYS_DDR_RAW_TIMING
  16. #define CONFIG_SYS_DRAM_SIZE 1024
  17. fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
  18. .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  19. .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  20. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  21. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
  22. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
  23. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
  24. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
  25. .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  26. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  27. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
  28. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
  29. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  30. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
  31. .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  32. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
  33. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  34. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  35. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  36. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  37. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  38. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
  39. .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  40. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  41. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  42. };
  43. fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
  44. .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  45. .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  46. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  47. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
  48. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
  49. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
  50. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
  51. .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  52. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  53. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
  54. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
  55. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  56. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
  57. .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  58. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
  59. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  60. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  61. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  62. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  63. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  64. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667,
  65. .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  66. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  67. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  68. };
  69. fixed_ddr_parm_t fixed_ddr_parm_0[] = {
  70. {750, 850, &ddr_cfg_regs_800},
  71. {607, 749, &ddr_cfg_regs_667},
  72. {0, 0, NULL}
  73. };
  74. unsigned long get_sdram_size(void)
  75. {
  76. struct cpu_type *cpu;
  77. phys_size_t ddr_size;
  78. cpu = gd->arch.cpu;
  79. /* P1014 and it's derivatives support max 16it DDR width */
  80. if (cpu->soc_ver == SVR_P1014)
  81. ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
  82. else
  83. ddr_size = CONFIG_SYS_DRAM_SIZE;
  84. return ddr_size;
  85. }
  86. /*
  87. * Fixed sdram init -- doesn't use serial presence detect.
  88. */
  89. phys_size_t fixed_sdram(void)
  90. {
  91. int i;
  92. char buf[32];
  93. fsl_ddr_cfg_regs_t ddr_cfg_regs;
  94. phys_size_t ddr_size;
  95. ulong ddr_freq, ddr_freq_mhz;
  96. struct cpu_type *cpu;
  97. #if defined(CONFIG_SYS_RAMBOOT)
  98. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  99. #endif
  100. ddr_freq = get_ddr_freq(0);
  101. ddr_freq_mhz = ddr_freq / 1000000;
  102. printf("Configuring DDR for %s MT/s data rate\n",
  103. strmhz(buf, ddr_freq));
  104. for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
  105. if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
  106. (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
  107. memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
  108. sizeof(ddr_cfg_regs));
  109. break;
  110. }
  111. }
  112. if (fixed_ddr_parm_0[i].max_freq == 0)
  113. panic("Unsupported DDR data rate %s MT/s data rate\n",
  114. strmhz(buf, ddr_freq));
  115. cpu = gd->arch.cpu;
  116. /* P1014 and it's derivatives support max 16bit DDR width */
  117. if (cpu->soc_ver == SVR_P1014) {
  118. ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
  119. ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
  120. /* divide SA and EA by two and then mask the rest so we don't
  121. * write to reserved fields */
  122. ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff;
  123. }
  124. ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  125. fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
  126. if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
  127. LAW_TRGT_IF_DDR_1) < 0) {
  128. printf("ERROR setting Local Access Windows for DDR\n");
  129. return 0;
  130. }
  131. return ddr_size;
  132. }
  133. #else /* CONFIG_SYS_DDR_RAW_TIMING */
  134. /*
  135. * Samsung K4B2G0846C-HCF8
  136. * The following timing are for "downshift"
  137. * i.e. to use CL9 part as CL7
  138. * otherwise, tAA, tRCD, tRP will be 13500ps
  139. * and tRC will be 49500ps
  140. */
  141. dimm_params_t ddr_raw_timing = {
  142. .n_ranks = 1,
  143. .rank_density = 1073741824u,
  144. .capacity = 1073741824u,
  145. .primary_sdram_width = 32,
  146. .ec_sdram_width = 0,
  147. .registered_dimm = 0,
  148. .mirrored_dimm = 0,
  149. .n_row_addr = 15,
  150. .n_col_addr = 10,
  151. .n_banks_per_sdram_device = 8,
  152. .edc_config = 0,
  153. .burst_lengths_bitmask = 0x0c,
  154. .tckmin_x_ps = 1875,
  155. .caslat_x = 0x1e << 4, /* 5,6,7,8 */
  156. .taa_ps = 13125,
  157. .twr_ps = 15000,
  158. .trcd_ps = 13125,
  159. .trrd_ps = 7500,
  160. .trp_ps = 13125,
  161. .tras_ps = 37500,
  162. .trc_ps = 50625,
  163. .trfc_ps = 160000,
  164. .twtr_ps = 7500,
  165. .trtp_ps = 7500,
  166. .refresh_rate_ps = 7800000,
  167. .tfaw_ps = 37500,
  168. };
  169. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  170. unsigned int controller_number,
  171. unsigned int dimm_number)
  172. {
  173. const char dimm_model[] = "Fixed DDR on board";
  174. if ((controller_number == 0) && (dimm_number == 0)) {
  175. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  176. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  177. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  178. }
  179. return 0;
  180. }
  181. void fsl_ddr_board_options(memctl_options_t *popts,
  182. dimm_params_t *pdimm,
  183. unsigned int ctrl_num)
  184. {
  185. struct cpu_type *cpu;
  186. int i;
  187. popts->clk_adjust = 6;
  188. popts->cpo_override = 0x1f;
  189. popts->write_data_delay = 2;
  190. popts->half_strength_driver_enable = 1;
  191. /* Write leveling override */
  192. popts->wrlvl_en = 1;
  193. popts->wrlvl_override = 1;
  194. popts->wrlvl_sample = 0xf;
  195. popts->wrlvl_start = 0x8;
  196. popts->trwt_override = 1;
  197. popts->trwt = 0;
  198. cpu = gd->arch.cpu;
  199. /* P1014 and it's derivatives support max 16it DDR width */
  200. if (cpu->soc_ver == SVR_P1014)
  201. popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
  202. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  203. popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  204. popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  205. }
  206. }
  207. #endif /* CONFIG_SYS_DDR_RAW_TIMING */