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- // SPDX-License-Identifier: GPL-2.0+
- /*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- */
- #include <init.h>
- #include <net.h>
- #include <asm/arch/clock.h>
- #include <asm/arch/iomux.h>
- #include <asm/arch/imx-regs.h>
- #include <asm/arch/crm_regs.h>
- #include <asm/arch/mx6ul_pins.h>
- #include <asm/arch/mx6-pins.h>
- #include <asm/arch/sys_proto.h>
- #include <asm/gpio.h>
- #include <asm/mach-imx/iomux-v3.h>
- #include <asm/mach-imx/boot_mode.h>
- #include <asm/mach-imx/mxc_i2c.h>
- #include <asm/io.h>
- #include <common.h>
- #include <env.h>
- #include <fsl_esdhc_imx.h>
- #include <i2c.h>
- #include <miiphy.h>
- #include <linux/delay.h>
- #include <linux/sizes.h>
- #include <mmc.h>
- #include <netdev.h>
- #include <power/pmic.h>
- #include <power/pfuze3000_pmic.h>
- #include "../common/pfuze.h"
- #include <usb.h>
- #include <usb/ehci-ci.h>
- DECLARE_GLOBAL_DATA_PTR;
- #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
- #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
- #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
- #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
- #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
- #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
- #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
- #ifdef CONFIG_DM_PMIC
- int power_init_board(void)
- {
- struct udevice *dev;
- int ret, dev_id, rev_id;
- unsigned int reg;
- ret = pmic_get("pfuze3000", &dev);
- if (ret == -ENODEV)
- return 0;
- if (ret != 0)
- return ret;
- dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
- rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
- printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
- /* disable Low Power Mode during standby mode */
- reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
- reg |= 0x1;
- pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
- /* SW1B step ramp up time from 2us to 4us/25mV */
- pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
- /* SW1B mode to APS/PFM */
- pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
- /* SW1B standby voltage set to 0.975V */
- pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
- return 0;
- }
- #endif
- int dram_init(void)
- {
- gd->ram_size = imx_ddr_size();
- return 0;
- }
- static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- };
- static void setup_iomux_uart(void)
- {
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- }
- #ifdef CONFIG_FSL_QSPI
- static int board_qspi_init(void)
- {
- /* Set the clock */
- enable_qspi_clk(0);
- return 0;
- }
- #endif
- #ifdef CONFIG_SPL_BUILD
- #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
- static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- };
- static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC2_BASE_ADDR, 0, 4},
- };
- int board_mmc_getcd(struct mmc *mmc)
- {
- return 1;
- }
- int board_mmc_init(struct bd_info *bis)
- {
- imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- }
- #endif
- #ifdef CONFIG_USB_EHCI_MX6
- #ifndef CONFIG_DM_USB
- #define USB_OTHERREGS_OFFSET 0x800
- #define UCTRL_PWR_POL (1 << 9)
- static iomux_v3_cfg_t const usb_otg_pads[] = {
- MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
- };
- /* At default the 3v3 enables the MIC2026 for VBUS power */
- static void setup_usb(void)
- {
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
- ARRAY_SIZE(usb_otg_pads));
- }
- int board_usb_phy_mode(int port)
- {
- if (port == 1)
- return USB_INIT_HOST;
- else
- return usb_phy_mode(port);
- }
- int board_ehci_hcd_init(int port)
- {
- u32 *usbnc_usb_ctrl;
- if (port > 1)
- return -EINVAL;
- usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
- port * 4);
- /* Set Power polarity */
- setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
- return 0;
- }
- #endif
- #endif
- #ifdef CONFIG_FEC_MXC
- static int setup_fec(int fec_id)
- {
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int ret;
- if (fec_id == 0) {
- /*
- * Use 50M anatop loopback REF_CLK1 for ENET1,
- * clear gpr1[13], set gpr1[17].
- */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
- IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
- } else {
- /*
- * Use 50M anatop loopback REF_CLK2 for ENET2,
- * clear gpr1[14], set gpr1[18].
- */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
- IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
- }
- ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
- if (ret)
- return ret;
- enable_enet_clk(1);
- return 0;
- }
- int board_phy_config(struct phy_device *phydev)
- {
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- return 0;
- }
- #endif
- #ifdef CONFIG_DM_VIDEO
- static iomux_v3_cfg_t const lcd_pads[] = {
- /* Use GPIO for Brightness adjustment, duty cycle = period. */
- MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
- };
- static int setup_lcd(void)
- {
- enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
- imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
- /* Reset the LCD */
- gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
- gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
- udelay(500);
- gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
- /* Set Brightness to high */
- gpio_request(IMX_GPIO_NR(1, 8), "backlight");
- gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
- return 0;
- }
- #else
- static inline int setup_lcd(void) { return 0; }
- #endif
- int board_early_init_f(void)
- {
- setup_iomux_uart();
- return 0;
- }
- int board_init(void)
- {
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- #ifdef CONFIG_FEC_MXC
- setup_fec(CONFIG_FEC_ENET_DEV);
- #endif
- #ifdef CONFIG_USB_EHCI_MX6
- #ifndef CONFIG_DM_USB
- setup_usb();
- #endif
- #endif
- #ifdef CONFIG_FSL_QSPI
- board_qspi_init();
- #endif
- return 0;
- }
- #ifdef CONFIG_CMD_BMODE
- static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
- {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
- {NULL, 0},
- };
- #endif
- int board_late_init(void)
- {
- #ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
- #endif
- #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- env_set("board_name", "EVK");
- if (is_mx6ul_9x9_evk())
- env_set("board_rev", "9X9");
- else
- env_set("board_rev", "14X14");
- #endif
- setup_lcd();
- return 0;
- }
- int checkboard(void)
- {
- if (is_mx6ul_9x9_evk())
- puts("Board: MX6UL 9x9 EVK\n");
- else
- puts("Board: MX6UL 14x14 EVK\n");
- return 0;
- }
- /*
- * Backlight off and reset LCD before OS handover
- */
- void board_preboot_os(void)
- {
- gpio_set_value(IMX_GPIO_NR(1, 8), 0);
- gpio_set_value(IMX_GPIO_NR(5, 9), 0);
- }
- #ifdef CONFIG_SPL_BUILD
- #include <linux/libfdt.h>
- #include <spl.h>
- #include <asm/arch/mx6-ddr.h>
- static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
- .grp_addds = 0x00000030,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_ddrpke = 0x00000000,
- .grp_ddrmode = 0x00020000,
- #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
- .grp_ddr_type = 0x00080000,
- #else
- .grp_ddr_type = 0x000c0000,
- #endif
- };
- #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
- static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_dqm0 = 0x00000030,
- .dram_dqm1 = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_odt0 = 0x00000000,
- .dram_odt1 = 0x00000000,
- .dram_sdba2 = 0x00000000,
- .dram_sdclk_0 = 0x00000030,
- .dram_sdqs0 = 0x00003030,
- .dram_sdqs1 = 0x00003030,
- .dram_reset = 0x00000030,
- };
- static struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00000000,
- .p0_mpdgctrl0 = 0x20000000,
- .p0_mprddlctl = 0x4040484f,
- .p0_mpwrdlctl = 0x40405247,
- .mpzqlp2ctl = 0x1b4700c7,
- };
- static struct mx6_lpddr2_cfg mem_ddr = {
- .mem_speed = 800,
- .density = 2,
- .width = 16,
- .banks = 4,
- .rowaddr = 14,
- .coladdr = 10,
- .trcd_lp = 1500,
- .trppb_lp = 1500,
- .trpab_lp = 2000,
- .trasmin = 4250,
- };
- struct mx6_ddr_sysinfo ddr_sysinfo = {
- .dsize = 0,
- .cs_density = 18,
- .ncs = 1,
- .cs1_mirror = 0,
- .walat = 0,
- .ralat = 5,
- .mif3_mode = 3,
- .bi_on = 1,
- .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
- .rtt_nom = 0,
- .sde_to_rst = 0, /* LPDDR2 does not need this field */
- .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
- .ddr_type = DDR_TYPE_LPDDR2,
- .refsel = 0, /* Refresh cycles at 64KHz */
- .refr = 3, /* 4 refresh commands per refresh cycle */
- };
- #else
- static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_dqm0 = 0x00000030,
- .dram_dqm1 = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_odt0 = 0x00000030,
- .dram_odt1 = 0x00000030,
- .dram_sdba2 = 0x00000000,
- .dram_sdclk_0 = 0x00000030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_reset = 0x00000030,
- };
- static struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00000000,
- .p0_mpdgctrl0 = 0x41570155,
- .p0_mprddlctl = 0x4040474A,
- .p0_mpwrdlctl = 0x40405550,
- };
- struct mx6_ddr_sysinfo ddr_sysinfo = {
- .dsize = 0,
- .cs_density = 20,
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 2,
- .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
- .walat = 0, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 0, /* Refresh cycles at 64KHz */
- .refr = 1, /* 2 refresh commands per refresh cycle */
- };
- static struct mx6_ddr3_cfg mem_ddr = {
- .mem_speed = 800,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 15,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
- };
- #endif
- static void ccgr_init(void)
- {
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- writel(0xFFFFFFFF, &ccm->CCGR0);
- writel(0xFFFFFFFF, &ccm->CCGR1);
- writel(0xFFFFFFFF, &ccm->CCGR2);
- writel(0xFFFFFFFF, &ccm->CCGR3);
- writel(0xFFFFFFFF, &ccm->CCGR4);
- writel(0xFFFFFFFF, &ccm->CCGR5);
- writel(0xFFFFFFFF, &ccm->CCGR6);
- writel(0xFFFFFFFF, &ccm->CCGR7);
- }
- static void spl_dram_init(void)
- {
- mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
- }
- void board_init_f(ulong dummy)
- {
- ccgr_init();
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
- /* iomux and setup of i2c */
- board_early_init_f();
- /* setup GP timer */
- timer_init();
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
- /* DDR initialization */
- spl_dram_init();
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
- }
- #endif
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