mx53loco.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  4. * Jason Liu <r64343@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/iomux-mx53.h>
  15. #include <asm/arch/clock.h>
  16. #include <env.h>
  17. #include <linux/errno.h>
  18. #include <asm/mach-imx/mx5_video.h>
  19. #include <netdev.h>
  20. #include <i2c.h>
  21. #include <input.h>
  22. #include <mmc.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <asm/gpio.h>
  25. #include <power/pmic.h>
  26. #include <dialog_pmic.h>
  27. #include <fsl_pmic.h>
  28. #include <linux/fb.h>
  29. #include <ipu_pixfmt.h>
  30. #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
  31. DECLARE_GLOBAL_DATA_PTR;
  32. u32 get_board_rev(void)
  33. {
  34. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  35. struct fuse_bank *bank = &iim->bank[0];
  36. struct fuse_bank0_regs *fuse =
  37. (struct fuse_bank0_regs *)bank->fuse_regs;
  38. int rev = readl(&fuse->gp[6]);
  39. if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
  40. rev = 0;
  41. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  42. }
  43. #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  44. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  45. static void setup_iomux_uart(void)
  46. {
  47. static const iomux_v3_cfg_t uart_pads[] = {
  48. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
  49. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
  50. };
  51. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  52. }
  53. #ifdef CONFIG_USB_EHCI_MX5
  54. int board_ehci_hcd_init(int port)
  55. {
  56. /* request VBUS power enable pin, GPIO7_8 */
  57. imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
  58. gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
  59. return 0;
  60. }
  61. #endif
  62. static void setup_iomux_fec(void)
  63. {
  64. static const iomux_v3_cfg_t fec_pads[] = {
  65. NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  66. PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  67. NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  68. NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  69. PAD_CTL_HYS | PAD_CTL_PKE),
  70. NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  71. PAD_CTL_HYS | PAD_CTL_PKE),
  72. NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
  73. NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
  74. NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  75. NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  76. PAD_CTL_HYS | PAD_CTL_PKE),
  77. NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  78. PAD_CTL_HYS | PAD_CTL_PKE),
  79. NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  80. PAD_CTL_HYS | PAD_CTL_PKE),
  81. };
  82. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  83. }
  84. #ifdef CONFIG_FSL_ESDHC_IMX
  85. struct fsl_esdhc_cfg esdhc_cfg[2] = {
  86. {MMC_SDHC1_BASE_ADDR},
  87. {MMC_SDHC3_BASE_ADDR},
  88. };
  89. int board_mmc_getcd(struct mmc *mmc)
  90. {
  91. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  92. int ret;
  93. imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
  94. gpio_direction_input(IMX_GPIO_NR(3, 11));
  95. imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
  96. gpio_direction_input(IMX_GPIO_NR(3, 13));
  97. if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  98. ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
  99. else
  100. ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
  101. return ret;
  102. }
  103. #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  104. PAD_CTL_PUS_100K_UP)
  105. #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
  106. PAD_CTL_DSE_HIGH)
  107. int board_mmc_init(struct bd_info *bis)
  108. {
  109. static const iomux_v3_cfg_t sd1_pads[] = {
  110. NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
  111. NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
  112. NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
  113. NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
  114. NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
  115. NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
  116. MX53_PAD_EIM_DA13__GPIO3_13,
  117. };
  118. static const iomux_v3_cfg_t sd2_pads[] = {
  119. NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
  120. SD_CMD_PAD_CTRL),
  121. NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
  122. NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
  123. NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
  124. NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
  125. NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
  126. NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
  127. NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
  128. NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
  129. NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
  130. MX53_PAD_EIM_DA11__GPIO3_11,
  131. };
  132. u32 index;
  133. int ret;
  134. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  135. esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  136. for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
  137. switch (index) {
  138. case 0:
  139. imx_iomux_v3_setup_multiple_pads(sd1_pads,
  140. ARRAY_SIZE(sd1_pads));
  141. break;
  142. case 1:
  143. imx_iomux_v3_setup_multiple_pads(sd2_pads,
  144. ARRAY_SIZE(sd2_pads));
  145. break;
  146. default:
  147. printf("Warning: you configured more ESDHC controller"
  148. "(%d) as supported by the board(2)\n",
  149. CONFIG_SYS_FSL_ESDHC_NUM);
  150. return -EINVAL;
  151. }
  152. ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  153. if (ret)
  154. return ret;
  155. }
  156. return 0;
  157. }
  158. #endif
  159. #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
  160. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  161. static void setup_iomux_i2c(void)
  162. {
  163. static const iomux_v3_cfg_t i2c1_pads[] = {
  164. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
  165. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
  166. };
  167. imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
  168. }
  169. static int power_init(void)
  170. {
  171. unsigned int val;
  172. int ret;
  173. struct pmic *p;
  174. if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
  175. ret = pmic_dialog_init(I2C_PMIC);
  176. if (ret)
  177. return ret;
  178. p = pmic_get("DIALOG_PMIC");
  179. if (!p)
  180. return -ENODEV;
  181. env_set("fdt_file", "imx53-qsb.dtb");
  182. /* Set VDDA to 1.25V */
  183. val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
  184. ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
  185. if (ret) {
  186. printf("Writing to BUCKCORE_REG failed: %d\n", ret);
  187. return ret;
  188. }
  189. pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
  190. val |= DA9052_SUPPLY_VBCOREGO;
  191. ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
  192. if (ret) {
  193. printf("Writing to SUPPLY_REG failed: %d\n", ret);
  194. return ret;
  195. }
  196. /* Set Vcc peripheral to 1.30V */
  197. ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
  198. if (ret) {
  199. printf("Writing to BUCKPRO_REG failed: %d\n", ret);
  200. return ret;
  201. }
  202. ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
  203. if (ret) {
  204. printf("Writing to SUPPLY_REG failed: %d\n", ret);
  205. return ret;
  206. }
  207. return ret;
  208. }
  209. if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
  210. ret = pmic_init(I2C_0);
  211. if (ret)
  212. return ret;
  213. p = pmic_get("FSL_PMIC");
  214. if (!p)
  215. return -ENODEV;
  216. env_set("fdt_file", "imx53-qsrb.dtb");
  217. /* Set VDDGP to 1.25V for 1GHz on SW1 */
  218. pmic_reg_read(p, REG_SW_0, &val);
  219. val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
  220. ret = pmic_reg_write(p, REG_SW_0, val);
  221. if (ret) {
  222. printf("Writing to REG_SW_0 failed: %d\n", ret);
  223. return ret;
  224. }
  225. /* Set VCC as 1.30V on SW2 */
  226. pmic_reg_read(p, REG_SW_1, &val);
  227. val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
  228. ret = pmic_reg_write(p, REG_SW_1, val);
  229. if (ret) {
  230. printf("Writing to REG_SW_1 failed: %d\n", ret);
  231. return ret;
  232. }
  233. /* Set global reset timer to 4s */
  234. pmic_reg_read(p, REG_POWER_CTL2, &val);
  235. val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
  236. ret = pmic_reg_write(p, REG_POWER_CTL2, val);
  237. if (ret) {
  238. printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
  239. return ret;
  240. }
  241. /* Set VUSBSEL and VUSBEN for USB PHY supply*/
  242. pmic_reg_read(p, REG_MODE_0, &val);
  243. val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
  244. ret = pmic_reg_write(p, REG_MODE_0, val);
  245. if (ret) {
  246. printf("Writing to REG_MODE_0 failed: %d\n", ret);
  247. return ret;
  248. }
  249. /* Set SWBST to 5V in auto mode */
  250. val = SWBST_AUTO;
  251. ret = pmic_reg_write(p, SWBST_CTRL, val);
  252. if (ret) {
  253. printf("Writing to SWBST_CTRL failed: %d\n", ret);
  254. return ret;
  255. }
  256. return ret;
  257. }
  258. return -1;
  259. }
  260. static void clock_1GHz(void)
  261. {
  262. int ret;
  263. u32 ref_clk = MXC_HCLK;
  264. /*
  265. * After increasing voltage to 1.25V, we can switch
  266. * CPU clock to 1GHz and DDR to 400MHz safely
  267. */
  268. ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
  269. if (ret)
  270. printf("CPU: Switch CPU clock to 1GHZ failed\n");
  271. ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
  272. ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
  273. if (ret)
  274. printf("CPU: Switch DDR clock to 400MHz failed\n");
  275. }
  276. int board_early_init_f(void)
  277. {
  278. setup_iomux_uart();
  279. setup_iomux_fec();
  280. setup_iomux_lcd();
  281. return 0;
  282. }
  283. /*
  284. * Do not overwrite the console
  285. * Use always serial for U-Boot console
  286. */
  287. int overwrite_console(void)
  288. {
  289. return 1;
  290. }
  291. int board_init(void)
  292. {
  293. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  294. mxc_set_sata_internal_clock();
  295. setup_iomux_i2c();
  296. return 0;
  297. }
  298. int board_late_init(void)
  299. {
  300. if (!power_init())
  301. clock_1GHz();
  302. return 0;
  303. }
  304. int checkboard(void)
  305. {
  306. puts("Board: MX53 LOCO\n");
  307. return 0;
  308. }