mx53ard.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <net.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/arch/crm_regs.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/iomux-mx53.h>
  14. #include <linux/errno.h>
  15. #include <netdev.h>
  16. #include <mmc.h>
  17. #include <fsl_esdhc_imx.h>
  18. #include <asm/gpio.h>
  19. #define ETHERNET_INT IMX_GPIO_NR(2, 31)
  20. DECLARE_GLOBAL_DATA_PTR;
  21. int dram_init(void)
  22. {
  23. u32 size1, size2;
  24. size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  25. size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  26. gd->ram_size = size1 + size2;
  27. return 0;
  28. }
  29. int dram_init_banksize(void)
  30. {
  31. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  32. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  33. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  34. gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  35. return 0;
  36. }
  37. #ifdef CONFIG_NAND_MXC
  38. static void setup_iomux_nand(void)
  39. {
  40. static const iomux_v3_cfg_t nand_pads[] = {
  41. NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
  42. PAD_CTL_DSE_HIGH),
  43. NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
  44. PAD_CTL_DSE_HIGH),
  45. NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
  46. PAD_CTL_PUS_100K_UP),
  47. NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
  48. PAD_CTL_DSE_HIGH),
  49. NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
  50. PAD_CTL_DSE_HIGH),
  51. NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
  52. PAD_CTL_PUS_100K_UP),
  53. NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
  54. PAD_CTL_DSE_HIGH),
  55. NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
  56. PAD_CTL_DSE_HIGH),
  57. NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
  58. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  59. NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
  60. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  61. NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
  62. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  63. NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
  64. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  65. NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
  66. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  67. NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
  68. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  69. NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
  70. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  71. NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
  72. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  73. };
  74. u32 i, reg;
  75. reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
  76. reg &= ~M4IF_GENP_WEIM_MM_MASK;
  77. __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
  78. for (i = 0x4; i < 0x94; i += 0x18) {
  79. reg = __raw_readl(WEIM_BASE_ADDR + i);
  80. reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
  81. __raw_writel(reg, WEIM_BASE_ADDR + i);
  82. }
  83. imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  84. }
  85. #else
  86. static void setup_iomux_nand(void)
  87. {
  88. }
  89. #endif
  90. #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  91. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  92. static void setup_iomux_uart(void)
  93. {
  94. static const iomux_v3_cfg_t uart_pads[] = {
  95. NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
  96. NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
  97. };
  98. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  99. }
  100. #ifdef CONFIG_FSL_ESDHC_IMX
  101. struct fsl_esdhc_cfg esdhc_cfg[2] = {
  102. {MMC_SDHC1_BASE_ADDR},
  103. {MMC_SDHC2_BASE_ADDR},
  104. };
  105. int board_mmc_getcd(struct mmc *mmc)
  106. {
  107. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  108. int ret;
  109. imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
  110. gpio_direction_input(IMX_GPIO_NR(1, 1));
  111. imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
  112. gpio_direction_input(IMX_GPIO_NR(1, 4));
  113. if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  114. ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
  115. else
  116. ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
  117. return ret;
  118. }
  119. #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  120. PAD_CTL_PUS_100K_UP)
  121. #define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
  122. #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
  123. PAD_CTL_DSE_HIGH)
  124. int board_mmc_init(struct bd_info *bis)
  125. {
  126. static const iomux_v3_cfg_t sd1_pads[] = {
  127. NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
  128. NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
  129. NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
  130. NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
  131. NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
  132. NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
  133. };
  134. static const iomux_v3_cfg_t sd2_pads[] = {
  135. NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
  136. NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
  137. NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
  138. NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
  139. NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
  140. NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
  141. NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
  142. NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
  143. NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
  144. NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
  145. };
  146. u32 index;
  147. int ret;
  148. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  149. esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  150. for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
  151. switch (index) {
  152. case 0:
  153. imx_iomux_v3_setup_multiple_pads(sd1_pads,
  154. ARRAY_SIZE(sd1_pads));
  155. break;
  156. case 1:
  157. imx_iomux_v3_setup_multiple_pads(sd2_pads,
  158. ARRAY_SIZE(sd2_pads));
  159. break;
  160. default:
  161. printf("Warning: you configured more ESDHC controller"
  162. "(%d) as supported by the board(2)\n",
  163. CONFIG_SYS_FSL_ESDHC_NUM);
  164. return -EINVAL;
  165. }
  166. ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  167. if (ret)
  168. return ret;
  169. }
  170. return 0;
  171. }
  172. #endif
  173. static void weim_smc911x_iomux(void)
  174. {
  175. static const iomux_v3_cfg_t weim_smc911x_pads[] = {
  176. /* Data bus */
  177. NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
  178. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  179. NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
  180. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  181. NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
  182. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  183. NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
  184. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  185. NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
  186. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  187. NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
  188. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  189. NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
  190. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  191. NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
  192. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  193. NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
  194. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  195. NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
  196. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  197. NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
  198. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  199. NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
  200. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  201. NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
  202. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  203. NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
  204. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  205. NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
  206. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  207. NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
  208. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  209. /* Address lines */
  210. NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
  211. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  212. NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
  213. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  214. NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
  215. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  216. NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
  217. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  218. NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
  219. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  220. NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
  221. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  222. NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
  223. PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  224. /* other EIM signals for ethernet */
  225. MX53_PAD_EIM_OE__EMI_WEIM_OE,
  226. MX53_PAD_EIM_RW__EMI_WEIM_RW,
  227. MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
  228. };
  229. /* ETHERNET_INT as GPIO2_31 */
  230. imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
  231. gpio_direction_input(ETHERNET_INT);
  232. /* WEIM bus */
  233. imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
  234. ARRAY_SIZE(weim_smc911x_pads));
  235. }
  236. static void weim_cs1_settings(void)
  237. {
  238. struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  239. writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
  240. writel(0x0, &weim_regs->cs1gcr2);
  241. writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
  242. writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
  243. writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
  244. writel(0x0, &weim_regs->cs1wcr2);
  245. writel(0x0, &weim_regs->wcr);
  246. set_chipselect_size(CS0_64M_CS1_64M);
  247. }
  248. int board_early_init_f(void)
  249. {
  250. setup_iomux_nand();
  251. setup_iomux_uart();
  252. return 0;
  253. }
  254. int board_init(void)
  255. {
  256. /* address of boot parameters */
  257. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  258. return 0;
  259. }
  260. int board_eth_init(struct bd_info *bis)
  261. {
  262. int rc = -ENODEV;
  263. weim_smc911x_iomux();
  264. weim_cs1_settings();
  265. #ifdef CONFIG_SMC911X
  266. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  267. #endif
  268. return rc;
  269. }
  270. int checkboard(void)
  271. {
  272. puts("Board: MX53ARD\n");
  273. return 0;
  274. }