mpc8641hpcn.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <log.h>
  8. #include <net.h>
  9. #include <pci.h>
  10. #include <asm/processor.h>
  11. #include <asm/immap_86xx.h>
  12. #include <asm/fsl_pci.h>
  13. #include <fsl_ddr_sdram.h>
  14. #include <asm/fsl_serdes.h>
  15. #include <asm/io.h>
  16. #include <linux/delay.h>
  17. #include <linux/libfdt.h>
  18. #include <fdt_support.h>
  19. #include <netdev.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. phys_size_t fixed_sdram(void);
  22. int checkboard(void)
  23. {
  24. u8 vboot;
  25. u8 *pixis_base = (u8 *)PIXIS_BASE;
  26. printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
  27. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  28. in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  29. in_8(pixis_base + PIXIS_PVER));
  30. vboot = in_8(pixis_base + PIXIS_VBOOT);
  31. if (vboot & PIXIS_VBOOT_FMAP)
  32. printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
  33. else
  34. puts ("Promjet\n");
  35. return 0;
  36. }
  37. int dram_init(void)
  38. {
  39. phys_size_t dram_size = 0;
  40. #if defined(CONFIG_SPD_EEPROM)
  41. dram_size = fsl_ddr_sdram();
  42. #else
  43. dram_size = fixed_sdram();
  44. #endif
  45. setup_ddr_bat(dram_size);
  46. debug(" DDR: ");
  47. gd->ram_size = dram_size;
  48. return 0;
  49. }
  50. #if !defined(CONFIG_SPD_EEPROM)
  51. /*
  52. * Fixed sdram init -- doesn't use serial presence detect.
  53. */
  54. phys_size_t
  55. fixed_sdram(void)
  56. {
  57. #if !defined(CONFIG_SYS_RAMBOOT)
  58. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  59. struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
  60. ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  61. ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  62. ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  63. ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  64. ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  65. ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  66. ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  67. ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  68. ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  69. ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  70. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  71. ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
  72. ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
  73. #if defined (CONFIG_DDR_ECC)
  74. ddr->err_disable = 0x0000008D;
  75. ddr->err_sbe = 0x00ff0000;
  76. #endif
  77. asm("sync;isync");
  78. udelay(500);
  79. #if defined (CONFIG_DDR_ECC)
  80. /* Enable ECC checking */
  81. ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
  82. #else
  83. ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
  84. ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
  85. #endif
  86. asm("sync; isync");
  87. udelay(500);
  88. #endif
  89. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  90. }
  91. #endif /* !defined(CONFIG_SPD_EEPROM) */
  92. void pci_init_board(void)
  93. {
  94. fsl_pcie_init_board(0);
  95. #ifdef CONFIG_PCIE1
  96. /*
  97. * Activate ULI1575 legacy chip by performing a fake
  98. * memory access. Needed to make ULI RTC work.
  99. */
  100. in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
  101. + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
  102. #endif /* CONFIG_PCIE1 */
  103. }
  104. #if defined(CONFIG_OF_BOARD_SETUP)
  105. int ft_board_setup(void *blob, struct bd_info *bd)
  106. {
  107. int off;
  108. u64 *tmp;
  109. int addrcells;
  110. ft_cpu_setup(blob, bd);
  111. FT_FSL_PCI_SETUP;
  112. /*
  113. * Warn if it looks like the device tree doesn't match u-boot.
  114. * This is just an estimation, based on the location of CCSR,
  115. * which is defined by the "reg" property in the soc node.
  116. */
  117. off = fdt_path_offset(blob, "/soc8641");
  118. addrcells = fdt_address_cells(blob, 0);
  119. tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
  120. if (tmp) {
  121. u64 addr;
  122. if (addrcells == 1)
  123. addr = *(u32 *)tmp;
  124. else
  125. addr = *tmp;
  126. if (addr != CONFIG_SYS_CCSRBAR_PHYS)
  127. printf("WARNING: The CCSRBAR address in your .dts "
  128. "does not match the address of the CCSR "
  129. "in u-boot. This means your .dts might "
  130. "be old.\n");
  131. }
  132. return 0;
  133. }
  134. #endif
  135. /*
  136. * get_board_sys_clk
  137. * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
  138. */
  139. unsigned long
  140. get_board_sys_clk(ulong dummy)
  141. {
  142. u8 i, go_bit, rd_clks;
  143. ulong val = 0;
  144. u8 *pixis_base = (u8 *)PIXIS_BASE;
  145. go_bit = in_8(pixis_base + PIXIS_VCTL);
  146. go_bit &= 0x01;
  147. rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
  148. rd_clks &= 0x1C;
  149. /*
  150. * Only if both go bit and the SCLK bit in VCFGEN0 are set
  151. * should we be using the AUX register. Remember, we also set the
  152. * GO bit to boot from the alternate bank on the on-board flash
  153. */
  154. if (go_bit) {
  155. if (rd_clks == 0x1c)
  156. i = in_8(pixis_base + PIXIS_AUX);
  157. else
  158. i = in_8(pixis_base + PIXIS_SPD);
  159. } else {
  160. i = in_8(pixis_base + PIXIS_SPD);
  161. }
  162. i &= 0x07;
  163. switch (i) {
  164. case 0:
  165. val = 33000000;
  166. break;
  167. case 1:
  168. val = 40000000;
  169. break;
  170. case 2:
  171. val = 50000000;
  172. break;
  173. case 3:
  174. val = 66000000;
  175. break;
  176. case 4:
  177. val = 83000000;
  178. break;
  179. case 5:
  180. val = 100000000;
  181. break;
  182. case 6:
  183. val = 134000000;
  184. break;
  185. case 7:
  186. val = 166000000;
  187. break;
  188. }
  189. return val;
  190. }
  191. int board_eth_init(struct bd_info *bis)
  192. {
  193. /* Initialize TSECs */
  194. cpu_eth_init(bis);
  195. return pci_eth_init(bis);
  196. }
  197. void board_reset(void)
  198. {
  199. u8 *pixis_base = (u8 *)PIXIS_BASE;
  200. out_8(pixis_base + PIXIS_RST, 0);
  201. while (1)
  202. ;
  203. }