mpc8610hpcd.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <net.h>
  10. #include <pci.h>
  11. #include <asm/processor.h>
  12. #include <asm/immap_86xx.h>
  13. #include <asm/fsl_pci.h>
  14. #include <fsl_ddr_sdram.h>
  15. #include <asm/fsl_serdes.h>
  16. #include <i2c.h>
  17. #include <asm/io.h>
  18. #include <linux/delay.h>
  19. #include <linux/libfdt.h>
  20. #include <fdt_support.h>
  21. #include <spd_sdram.h>
  22. #include <netdev.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. void sdram_init(void);
  25. phys_size_t fixed_sdram(void);
  26. int mpc8610hpcd_diu_init(void);
  27. /* called before any console output */
  28. int board_early_init_f(void)
  29. {
  30. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  31. volatile ccsr_gur_t *gur = &immap->im_gur;
  32. gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
  33. return 0;
  34. }
  35. int misc_init_r(void)
  36. {
  37. u8 tmp_val, version;
  38. u8 *pixis_base = (u8 *)PIXIS_BASE;
  39. /*Do not use 8259PIC*/
  40. tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
  41. out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
  42. /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
  43. version = in_8(pixis_base + PIXIS_PVER);
  44. if(version >= 0x07) {
  45. tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
  46. out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
  47. }
  48. /* Using this for DIU init before the driver in linux takes over
  49. * Enable the TFP410 Encoder (I2C address 0x38)
  50. */
  51. tmp_val = 0xBF;
  52. i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  53. /* Verify if enabled */
  54. tmp_val = 0;
  55. i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  56. debug("DVI Encoder Read: 0x%02x\n", tmp_val);
  57. tmp_val = 0x10;
  58. i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  59. /* Verify if enabled */
  60. tmp_val = 0;
  61. i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  62. debug("DVI Encoder Read: 0x%02x\n", tmp_val);
  63. return 0;
  64. }
  65. int checkboard(void)
  66. {
  67. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  68. volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
  69. u8 *pixis_base = (u8 *)PIXIS_BASE;
  70. printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
  71. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  72. in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  73. in_8(pixis_base + PIXIS_PVER));
  74. /*
  75. * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
  76. * bank and LBMAP=00 is the alternate bank. However, the pixis
  77. * altbank code can only set bits, not clear them, so we treat 00 as
  78. * the normal bank and 11 as the alternate.
  79. */
  80. switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
  81. case 0:
  82. puts("vBank: Standard\n");
  83. break;
  84. case 0x40:
  85. puts("Promjet\n");
  86. break;
  87. case 0x80:
  88. puts("NAND\n");
  89. break;
  90. case 0xC0:
  91. puts("vBank: Alternate\n");
  92. break;
  93. }
  94. mcm->abcr |= 0x00010000; /* 0 */
  95. mcm->hpmr3 = 0x80000008; /* 4c */
  96. mcm->hpmr0 = 0;
  97. mcm->hpmr1 = 0;
  98. mcm->hpmr2 = 0;
  99. mcm->hpmr4 = 0;
  100. mcm->hpmr5 = 0;
  101. return 0;
  102. }
  103. int dram_init(void)
  104. {
  105. phys_size_t dram_size = 0;
  106. #if defined(CONFIG_SPD_EEPROM)
  107. dram_size = fsl_ddr_sdram();
  108. #else
  109. dram_size = fixed_sdram();
  110. #endif
  111. setup_ddr_bat(dram_size);
  112. debug(" DDR: ");
  113. gd->ram_size = dram_size;
  114. return 0;
  115. }
  116. #if !defined(CONFIG_SPD_EEPROM)
  117. /*
  118. * Fixed sdram init -- doesn't use serial presence detect.
  119. */
  120. phys_size_t fixed_sdram(void)
  121. {
  122. #if !defined(CONFIG_SYS_RAMBOOT)
  123. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  124. struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
  125. uint d_init;
  126. ddr->cs0_bnds = 0x0000001f;
  127. ddr->cs0_config = 0x80010202;
  128. ddr->timing_cfg_3 = 0x00000000;
  129. ddr->timing_cfg_0 = 0x00260802;
  130. ddr->timing_cfg_1 = 0x3935d322;
  131. ddr->timing_cfg_2 = 0x14904cc8;
  132. ddr->sdram_mode = 0x00480432;
  133. ddr->sdram_mode_2 = 0x00000000;
  134. ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
  135. ddr->sdram_data_init = 0xDEADBEEF;
  136. ddr->sdram_clk_cntl = 0x03800000;
  137. ddr->sdram_cfg_2 = 0x04400010;
  138. #if defined(CONFIG_DDR_ECC)
  139. ddr->err_int_en = 0x0000000d;
  140. ddr->err_disable = 0x00000000;
  141. ddr->err_sbe = 0x00010000;
  142. #endif
  143. asm("sync;isync");
  144. udelay(500);
  145. ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
  146. #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  147. d_init = 1;
  148. debug("DDR - 1st controller: memory initializing\n");
  149. /*
  150. * Poll until memory is initialized.
  151. * 512 Meg at 400 might hit this 200 times or so.
  152. */
  153. while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
  154. udelay(1000);
  155. debug("DDR: memory initialized\n\n");
  156. asm("sync; isync");
  157. udelay(500);
  158. #endif
  159. return 512 * 1024 * 1024;
  160. #endif
  161. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  162. }
  163. #endif
  164. #if defined(CONFIG_PCI)
  165. /*
  166. * Initialize PCI Devices, report devices found.
  167. */
  168. #ifndef CONFIG_PCI_PNP
  169. static struct pci_config_table pci_fsl86xxads_config_table[] = {
  170. {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  171. PCI_IDSEL_NUMBER, PCI_ANY_ID,
  172. pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
  173. PCI_ENET0_MEMADDR,
  174. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
  175. {}
  176. };
  177. #endif
  178. static struct pci_controller pci1_hose;
  179. #endif /* CONFIG_PCI */
  180. void pci_init_board(void)
  181. {
  182. volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
  183. volatile ccsr_gur_t *gur = &immap->im_gur;
  184. struct fsl_pci_info pci_info;
  185. u32 devdisr;
  186. int first_free_busno;
  187. int pci_agent;
  188. devdisr = in_be32(&gur->devdisr);
  189. first_free_busno = fsl_pcie_init_board(0);
  190. #ifdef CONFIG_PCI1
  191. if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
  192. SET_STD_PCI_INFO(pci_info, 1);
  193. set_next_law(pci_info.mem_phys,
  194. law_size_bits(pci_info.mem_size), pci_info.law);
  195. set_next_law(pci_info.io_phys,
  196. law_size_bits(pci_info.io_size), pci_info.law);
  197. pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
  198. printf("PCI: connected to PCI slots as %s" \
  199. " (base address %lx)\n",
  200. pci_agent ? "Agent" : "Host",
  201. pci_info.regs);
  202. #ifndef CONFIG_PCI_PNP
  203. pci1_hose.config_table = pci_mpc86xxcts_config_table;
  204. #endif
  205. first_free_busno = fsl_pci_init_port(&pci_info,
  206. &pci1_hose, first_free_busno);
  207. } else {
  208. printf("PCI: disabled\n");
  209. }
  210. puts("\n");
  211. #else
  212. setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
  213. #endif
  214. fsl_pcie_init_board(first_free_busno);
  215. }
  216. #if defined(CONFIG_OF_BOARD_SETUP)
  217. int ft_board_setup(void *blob, struct bd_info *bd)
  218. {
  219. ft_cpu_setup(blob, bd);
  220. FT_FSL_PCI_SETUP;
  221. return 0;
  222. }
  223. #endif
  224. /*
  225. * get_board_sys_clk
  226. * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
  227. */
  228. unsigned long
  229. get_board_sys_clk(ulong dummy)
  230. {
  231. u8 i;
  232. ulong val = 0;
  233. u8 *pixis_base = (u8 *)PIXIS_BASE;
  234. i = in_8(pixis_base + PIXIS_SPD);
  235. i &= 0x07;
  236. switch (i) {
  237. case 0:
  238. val = 33333000;
  239. break;
  240. case 1:
  241. val = 39999600;
  242. break;
  243. case 2:
  244. val = 49999500;
  245. break;
  246. case 3:
  247. val = 66666000;
  248. break;
  249. case 4:
  250. val = 83332500;
  251. break;
  252. case 5:
  253. val = 99999000;
  254. break;
  255. case 6:
  256. val = 133332000;
  257. break;
  258. case 7:
  259. val = 166665000;
  260. break;
  261. }
  262. return val;
  263. }
  264. int board_eth_init(struct bd_info *bis)
  265. {
  266. return pci_eth_init(bis);
  267. }
  268. void board_reset(void)
  269. {
  270. u8 *pixis_base = (u8 *)PIXIS_BASE;
  271. out_8(pixis_base + PIXIS_RST, 0);
  272. while (1)
  273. ;
  274. }