mpc8544ds.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <pci.h>
  10. #include <asm/processor.h>
  11. #include <asm/mmu.h>
  12. #include <asm/immap_85xx.h>
  13. #include <asm/fsl_pci.h>
  14. #include <fsl_ddr_sdram.h>
  15. #include <asm/fsl_serdes.h>
  16. #include <asm/io.h>
  17. #include <miiphy.h>
  18. #include <linux/libfdt.h>
  19. #include <fdt_support.h>
  20. #include <fsl_mdio.h>
  21. #include <tsec.h>
  22. #include <netdev.h>
  23. #include "../common/sgmii_riser.h"
  24. int checkboard (void)
  25. {
  26. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  27. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  28. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  29. u8 vboot;
  30. u8 *pixis_base = (u8 *)PIXIS_BASE;
  31. if ((uint)&gur->porpllsr != 0xe00e0000) {
  32. printf("immap size error %lx\n",(ulong)&gur->porpllsr);
  33. }
  34. printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
  35. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  36. in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  37. in_8(pixis_base + PIXIS_PVER));
  38. vboot = in_8(pixis_base + PIXIS_VBOOT);
  39. if (vboot & PIXIS_VBOOT_FMAP)
  40. printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
  41. else
  42. puts ("Promjet\n");
  43. lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
  44. lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
  45. ecm->eedr = 0xffffffff; /* Clear ecm errors */
  46. ecm->eeer = 0xffffffff; /* Enable ecm errors */
  47. return 0;
  48. }
  49. #ifdef CONFIG_PCI1
  50. static struct pci_controller pci1_hose;
  51. #endif
  52. #ifdef CONFIG_PCIE3
  53. static struct pci_controller pcie3_hose;
  54. #endif
  55. void pci_init_board(void)
  56. {
  57. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  58. struct fsl_pci_info pci_info;
  59. u32 devdisr, pordevsr, io_sel;
  60. u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
  61. int first_free_busno = 0;
  62. int pcie_ep, pcie_configured;
  63. devdisr = in_be32(&gur->devdisr);
  64. pordevsr = in_be32(&gur->pordevsr);
  65. porpllsr = in_be32(&gur->porpllsr);
  66. io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
  67. debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
  68. puts("\n");
  69. #ifdef CONFIG_PCIE3
  70. pcie_configured = is_serdes_configured(PCIE3);
  71. if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
  72. /* contains both PCIE3 MEM & IO space */
  73. set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
  74. LAW_TRGT_IF_PCIE_3);
  75. SET_STD_PCIE_INFO(pci_info, 3);
  76. pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
  77. /* outbound memory */
  78. pci_set_region(&pcie3_hose.regions[0],
  79. CONFIG_SYS_PCIE3_MEM_BUS2,
  80. CONFIG_SYS_PCIE3_MEM_PHYS2,
  81. CONFIG_SYS_PCIE3_MEM_SIZE2,
  82. PCI_REGION_MEM);
  83. pcie3_hose.region_count = 1;
  84. printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
  85. pcie_ep ? "Endpoint" : "Root Complex",
  86. pci_info.regs);
  87. first_free_busno = fsl_pci_init_port(&pci_info,
  88. &pcie3_hose, first_free_busno);
  89. /*
  90. * Activate ULI1575 legacy chip by performing a fake
  91. * memory access. Needed to make ULI RTC work.
  92. */
  93. in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
  94. } else {
  95. printf("PCIE3: disabled\n");
  96. }
  97. puts("\n");
  98. #else
  99. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
  100. #endif
  101. #ifdef CONFIG_PCIE1
  102. SET_STD_PCIE_INFO(pci_info, 1);
  103. first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
  104. #else
  105. setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
  106. #endif
  107. #ifdef CONFIG_PCIE2
  108. SET_STD_PCIE_INFO(pci_info, 2);
  109. first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
  110. #else
  111. setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
  112. #endif
  113. #ifdef CONFIG_PCI1
  114. pci_speed = 66666000;
  115. pci_32 = 1;
  116. pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
  117. pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
  118. if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
  119. SET_STD_PCI_INFO(pci_info, 1);
  120. set_next_law(pci_info.mem_phys,
  121. law_size_bits(pci_info.mem_size), pci_info.law);
  122. set_next_law(pci_info.io_phys,
  123. law_size_bits(pci_info.io_size), pci_info.law);
  124. pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
  125. printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
  126. (pci_32) ? 32 : 64,
  127. (pci_speed == 33333000) ? "33" :
  128. (pci_speed == 66666000) ? "66" : "unknown",
  129. pci_clk_sel ? "sync" : "async",
  130. pci_agent ? "agent" : "host",
  131. pci_arb ? "arbiter" : "external-arbiter",
  132. pci_info.regs);
  133. first_free_busno = fsl_pci_init_port(&pci_info,
  134. &pci1_hose, first_free_busno);
  135. } else {
  136. printf("PCI: disabled\n");
  137. }
  138. puts("\n");
  139. #else
  140. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
  141. #endif
  142. }
  143. int last_stage_init(void)
  144. {
  145. return 0;
  146. }
  147. unsigned long
  148. get_board_sys_clk(ulong dummy)
  149. {
  150. u8 i, go_bit, rd_clks;
  151. ulong val = 0;
  152. u8 *pixis_base = (u8 *)PIXIS_BASE;
  153. go_bit = in_8(pixis_base + PIXIS_VCTL);
  154. go_bit &= 0x01;
  155. rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
  156. rd_clks &= 0x1C;
  157. /*
  158. * Only if both go bit and the SCLK bit in VCFGEN0 are set
  159. * should we be using the AUX register. Remember, we also set the
  160. * GO bit to boot from the alternate bank on the on-board flash
  161. */
  162. if (go_bit) {
  163. if (rd_clks == 0x1c)
  164. i = in_8(pixis_base + PIXIS_AUX);
  165. else
  166. i = in_8(pixis_base + PIXIS_SPD);
  167. } else {
  168. i = in_8(pixis_base + PIXIS_SPD);
  169. }
  170. i &= 0x07;
  171. switch (i) {
  172. case 0:
  173. val = 33333333;
  174. break;
  175. case 1:
  176. val = 40000000;
  177. break;
  178. case 2:
  179. val = 50000000;
  180. break;
  181. case 3:
  182. val = 66666666;
  183. break;
  184. case 4:
  185. val = 83000000;
  186. break;
  187. case 5:
  188. val = 100000000;
  189. break;
  190. case 6:
  191. val = 133333333;
  192. break;
  193. case 7:
  194. val = 166666666;
  195. break;
  196. }
  197. return val;
  198. }
  199. #define MIIM_CIS8204_SLED_CON 0x1b
  200. #define MIIM_CIS8204_SLEDCON_INIT 0x1115
  201. /*
  202. * Hack to write all 4 PHYs with the LED values
  203. */
  204. int board_phy_config(struct phy_device *phydev)
  205. {
  206. static int do_once;
  207. uint phyid;
  208. struct mii_dev *bus = phydev->bus;
  209. if (phydev->drv->config)
  210. phydev->drv->config(phydev);
  211. if (do_once)
  212. return 0;
  213. for (phyid = 0; phyid < 4; phyid++)
  214. bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
  215. MIIM_CIS8204_SLEDCON_INIT);
  216. do_once = 1;
  217. return 0;
  218. }
  219. int board_eth_init(struct bd_info *bis)
  220. {
  221. #ifdef CONFIG_TSEC_ENET
  222. struct fsl_pq_mdio_info mdio_info;
  223. struct tsec_info_struct tsec_info[2];
  224. int num = 0;
  225. #ifdef CONFIG_TSEC1
  226. SET_STD_TSEC_INFO(tsec_info[num], 1);
  227. if (is_serdes_configured(SGMII_TSEC1)) {
  228. puts("eTSEC1 is in sgmii mode.\n");
  229. tsec_info[num].flags |= TSEC_SGMII;
  230. }
  231. num++;
  232. #endif
  233. #ifdef CONFIG_TSEC3
  234. SET_STD_TSEC_INFO(tsec_info[num], 3);
  235. if (is_serdes_configured(SGMII_TSEC3)) {
  236. puts("eTSEC3 is in sgmii mode.\n");
  237. tsec_info[num].flags |= TSEC_SGMII;
  238. }
  239. num++;
  240. #endif
  241. if (!num) {
  242. printf("No TSECs initialized\n");
  243. return 0;
  244. }
  245. if (is_serdes_configured(SGMII_TSEC1) ||
  246. is_serdes_configured(SGMII_TSEC3)) {
  247. fsl_sgmii_riser_init(tsec_info, num);
  248. }
  249. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  250. mdio_info.name = DEFAULT_MII_NAME;
  251. fsl_pq_mdio_init(bis, &mdio_info);
  252. tsec_eth_init(bis, tsec_info, num);
  253. #endif
  254. return pci_eth_init(bis);
  255. }
  256. #if defined(CONFIG_OF_BOARD_SETUP)
  257. int ft_board_setup(void *blob, struct bd_info *bd)
  258. {
  259. ft_cpu_setup(blob, bd);
  260. FT_FSL_PCI_SETUP;
  261. #ifdef CONFIG_FSL_SGMII_RISER
  262. fsl_sgmii_riser_fdt_fixup(blob);
  263. #endif
  264. return 0;
  265. }
  266. #endif