sdram.c 3.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
  4. *
  5. * Authors: Nick.Spence@freescale.com
  6. * Wilson.Lo@freescale.com
  7. * scottwood@freescale.com
  8. */
  9. #include <common.h>
  10. #include <init.h>
  11. #include <mpc83xx.h>
  12. #include <spd_sdram.h>
  13. #include <linux/delay.h>
  14. #include <asm/bitops.h>
  15. #include <asm/io.h>
  16. #include <asm/processor.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  19. static void resume_from_sleep(void)
  20. {
  21. u32 magic = *(u32 *)0;
  22. typedef void (*func_t)(void);
  23. func_t resume = *(func_t *)4;
  24. if (magic == 0xf5153ae5)
  25. resume();
  26. gd->flags &= ~GD_FLG_SILENT;
  27. puts("\nResume from sleep failed: bad magic word\n");
  28. }
  29. #endif
  30. /* Fixed sdram init -- doesn't use serial presence detect.
  31. *
  32. * This is useful for faster booting in configs where the RAM is unlikely
  33. * to be changed, or for things like NAND booting where space is tight.
  34. */
  35. static long fixed_sdram(void)
  36. {
  37. u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  38. #ifndef CONFIG_SYS_RAMBOOT
  39. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  40. u32 msize_log2 = __ilog2(msize);
  41. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  42. im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
  43. im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  44. /*
  45. * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  46. * or the DDR2 controller may fail to initialize correctly.
  47. */
  48. __udelay(50000);
  49. #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  50. #warning Chip select bounds is only configurable in 16MB increments
  51. #endif
  52. im->ddr.csbnds[0].csbnds =
  53. ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  54. (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
  55. CSBNDS_EA);
  56. im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  57. /* Currently we use only one CS, so disable the other bank. */
  58. im->ddr.cs_config[1] = 0;
  59. im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
  60. im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  61. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  62. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  63. im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  64. #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  65. if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  66. im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
  67. else
  68. #endif
  69. im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
  70. im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
  71. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  72. im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
  73. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  74. sync();
  75. /* enable DDR controller */
  76. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  77. #endif
  78. return msize;
  79. }
  80. int dram_init(void)
  81. {
  82. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  83. volatile fsl_lbc_t *lbc = &im->im_lbc;
  84. u32 msize;
  85. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  86. return -ENXIO;
  87. /* DDR SDRAM - Main SODIMM */
  88. msize = fixed_sdram();
  89. /* Local Bus setup lbcr and mrtpr */
  90. lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
  91. /* LB refresh timer prescal, 266MHz/32 */
  92. lbc->mrtpr = 0x20000000;
  93. sync();
  94. #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  95. if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  96. resume_from_sleep();
  97. #endif
  98. /* return total bus SDRAM size(bytes) -- DDR */
  99. gd->ram_size = msize;
  100. return 0;
  101. }