ls2080a.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <malloc.h>
  8. #include <errno.h>
  9. #include <net.h>
  10. #include <netdev.h>
  11. #include <fsl_ifc.h>
  12. #include <fsl_ddr.h>
  13. #include <asm/io.h>
  14. #include <fdt_support.h>
  15. #include <linux/libfdt.h>
  16. #include <fsl-mc/fsl_mc.h>
  17. #include <env_internal.h>
  18. #include <asm/arch/soc.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. int board_init(void)
  21. {
  22. init_final_memctl_regs();
  23. #ifdef CONFIG_ENV_IS_NOWHERE
  24. gd->env_addr = (ulong)&default_environment[0];
  25. #endif
  26. return 0;
  27. }
  28. int board_early_init_f(void)
  29. {
  30. fsl_lsch3_early_init_f();
  31. return 0;
  32. }
  33. void detail_board_ddr_info(void)
  34. {
  35. puts("\nDDR ");
  36. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  37. print_ddr_info(0);
  38. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  39. if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
  40. puts("\nDP-DDR ");
  41. print_size(gd->bd->bi_dram[2].size, "");
  42. print_ddr_info(CONFIG_DP_DDR_CTRL);
  43. }
  44. #endif
  45. }
  46. int board_eth_init(struct bd_info *bis)
  47. {
  48. int error = 0;
  49. #ifdef CONFIG_SMC91111
  50. error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
  51. #endif
  52. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  53. error = cpu_eth_init(bis);
  54. #endif
  55. return error;
  56. }
  57. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  58. void fdt_fixup_board_enet(void *fdt)
  59. {
  60. int offset;
  61. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  62. /*
  63. * TODO: Remove this when backward compatibility
  64. * with old DT node (/fsl-mc) is no longer needed.
  65. */
  66. if (offset < 0)
  67. offset = fdt_path_offset(fdt, "/fsl-mc");
  68. if (offset < 0) {
  69. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  70. __func__, offset);
  71. return;
  72. }
  73. if (get_mc_boot_status() == 0 &&
  74. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
  75. fdt_status_okay(fdt, offset);
  76. else
  77. fdt_status_fail(fdt, offset);
  78. }
  79. void board_quiesce_devices(void)
  80. {
  81. fsl_mc_ldpaa_exit(gd->bd);
  82. }
  83. #endif
  84. #ifdef CONFIG_OF_BOARD_SETUP
  85. int ft_board_setup(void *blob, struct bd_info *bd)
  86. {
  87. u64 base[CONFIG_NR_DRAM_BANKS];
  88. u64 size[CONFIG_NR_DRAM_BANKS];
  89. ft_cpu_setup(blob, bd);
  90. /* fixup DT for the two GPP DDR banks */
  91. base[0] = gd->bd->bi_dram[0].start;
  92. size[0] = gd->bd->bi_dram[0].size;
  93. base[1] = gd->bd->bi_dram[1].start;
  94. size[1] = gd->bd->bi_dram[1].size;
  95. #ifdef CONFIG_RESV_RAM
  96. /* reduce size if reserved memory is within this bank */
  97. if (gd->arch.resv_ram >= base[0] &&
  98. gd->arch.resv_ram < base[0] + size[0])
  99. size[0] = gd->arch.resv_ram - base[0];
  100. else if (gd->arch.resv_ram >= base[1] &&
  101. gd->arch.resv_ram < base[1] + size[1])
  102. size[1] = gd->arch.resv_ram - base[1];
  103. #endif
  104. fdt_fixup_memory_banks(blob, base, size, 2);
  105. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  106. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  107. fdt_fixup_board_enet(blob);
  108. #endif
  109. return 0;
  110. }
  111. #endif
  112. #if defined(CONFIG_RESET_PHY_R)
  113. void reset_phy(void)
  114. {
  115. }
  116. #endif
  117. #ifdef CONFIG_TFABOOT
  118. void *env_sf_get_env_addr(void)
  119. {
  120. return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET);
  121. }
  122. #endif