ddr.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. #include <log.h>
  9. #include <asm/arch/soc.h>
  10. #include <asm/arch/clock.h>
  11. #include "ddr.h"
  12. DECLARE_GLOBAL_DATA_PTR;
  13. void fsl_ddr_board_options(memctl_options_t *popts,
  14. dimm_params_t *pdimm,
  15. unsigned int ctrl_num)
  16. {
  17. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  18. ulong ddr_freq;
  19. if (ctrl_num > 3) {
  20. printf("Not supported controller number %d\n", ctrl_num);
  21. return;
  22. }
  23. if (!pdimm->n_ranks)
  24. return;
  25. /*
  26. * we use identical timing for all slots. If needed, change the code
  27. * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  28. */
  29. if (popts->registered_dimm_en)
  30. pbsp = rdimms[ctrl_num];
  31. else
  32. pbsp = udimms[ctrl_num];
  33. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  34. * freqency and n_banks specified in board_specific_parameters table.
  35. */
  36. ddr_freq = get_ddr_freq(0) / 1000000;
  37. while (pbsp->datarate_mhz_high) {
  38. if (pbsp->n_ranks == pdimm->n_ranks &&
  39. (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  40. if (ddr_freq <= pbsp->datarate_mhz_high) {
  41. popts->clk_adjust = pbsp->clk_adjust;
  42. popts->wrlvl_start = pbsp->wrlvl_start;
  43. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  44. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  45. goto found;
  46. }
  47. pbsp_highest = pbsp;
  48. }
  49. pbsp++;
  50. }
  51. if (pbsp_highest) {
  52. printf("Error: board specific timing not found for data rate %lu MT/s\n"
  53. "Trying to use the highest speed (%u) parameters\n",
  54. ddr_freq, pbsp_highest->datarate_mhz_high);
  55. popts->clk_adjust = pbsp_highest->clk_adjust;
  56. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  57. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  58. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  59. } else {
  60. panic("DIMM is not supported by this board");
  61. }
  62. found:
  63. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  64. "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  65. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  66. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  67. pbsp->wrlvl_ctl_3);
  68. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  69. if (ctrl_num == CONFIG_DP_DDR_CTRL) {
  70. /* force DDR bus width to 32 bits */
  71. popts->data_bus_width = 1;
  72. popts->otf_burst_chop_en = 0;
  73. popts->burst_length = DDR_BL8;
  74. popts->bstopre = 0; /* enable auto precharge */
  75. }
  76. #endif
  77. /*
  78. * Factors to consider for half-strength driver enable:
  79. * - number of DIMMs installed
  80. */
  81. popts->half_strength_driver_enable = 1;
  82. /*
  83. * Write leveling override
  84. */
  85. popts->wrlvl_override = 1;
  86. popts->wrlvl_sample = 0xf;
  87. /*
  88. * Rtt and Rtt_WR override
  89. */
  90. popts->rtt_override = 0;
  91. /* Enable ZQ calibration */
  92. popts->zq_en = 1;
  93. #ifdef CONFIG_SYS_FSL_DDR4
  94. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  95. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  96. DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
  97. #else
  98. /* DHC_EN =1, ODT = 75 Ohm */
  99. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  100. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  101. #endif
  102. }
  103. #ifdef CONFIG_SYS_DDR_RAW_TIMING
  104. dimm_params_t ddr_raw_timing = {
  105. .n_ranks = 2,
  106. .rank_density = 1073741824u,
  107. .capacity = 2147483648,
  108. .primary_sdram_width = 64,
  109. .ec_sdram_width = 0,
  110. .registered_dimm = 0,
  111. .mirrored_dimm = 0,
  112. .n_row_addr = 14,
  113. .n_col_addr = 10,
  114. .n_banks_per_sdram_device = 8,
  115. .edc_config = 0,
  116. .burst_lengths_bitmask = 0x0c,
  117. .tckmin_x_ps = 937,
  118. .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
  119. .taa_ps = 13090,
  120. .twr_ps = 15000,
  121. .trcd_ps = 13090,
  122. .trrd_ps = 5000,
  123. .trp_ps = 13090,
  124. .tras_ps = 33000,
  125. .trc_ps = 46090,
  126. .trfc_ps = 160000,
  127. .twtr_ps = 7500,
  128. .trtp_ps = 7500,
  129. .refresh_rate_ps = 7800000,
  130. .tfaw_ps = 25000,
  131. };
  132. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  133. unsigned int controller_number,
  134. unsigned int dimm_number)
  135. {
  136. const char dimm_model[] = "Fixed DDR on board";
  137. if (((controller_number == 0) && (dimm_number == 0)) ||
  138. ((controller_number == 1) && (dimm_number == 0))) {
  139. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  140. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  141. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  142. }
  143. return 0;
  144. }
  145. #endif
  146. int fsl_initdram(void)
  147. {
  148. puts("Initializing DDR....");
  149. puts("using SPD\n");
  150. gd->ram_size = fsl_ddr_sdram();
  151. return 0;
  152. }