ddr.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. #include <log.h>
  9. #include <asm/arch/soc.h>
  10. #include <asm/arch/clock.h>
  11. #include "ddr.h"
  12. DECLARE_GLOBAL_DATA_PTR;
  13. #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  14. static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts)
  15. {
  16. int vdd;
  17. vdd = get_core_volt_from_fuse();
  18. /* Nothing to do for silicons doesn't support VID */
  19. if (vdd < 0)
  20. return;
  21. if (vdd == 900) {
  22. popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN;
  23. debug("VID: configure DDR to support 900 mV\n");
  24. }
  25. }
  26. #endif
  27. void fsl_ddr_board_options(memctl_options_t *popts,
  28. dimm_params_t *pdimm,
  29. unsigned int ctrl_num)
  30. {
  31. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  32. ulong ddr_freq;
  33. if (ctrl_num > 1) {
  34. printf("Not supported controller number %d\n", ctrl_num);
  35. return;
  36. }
  37. if (!pdimm->n_ranks)
  38. return;
  39. /*
  40. * we use identical timing for all slots. If needed, change the code
  41. * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  42. */
  43. pbsp = udimms[0];
  44. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  45. * freqency and n_banks specified in board_specific_parameters table.
  46. */
  47. ddr_freq = get_ddr_freq(0) / 1000000;
  48. while (pbsp->datarate_mhz_high) {
  49. if (pbsp->n_ranks == pdimm->n_ranks) {
  50. if (ddr_freq <= pbsp->datarate_mhz_high) {
  51. popts->clk_adjust = pbsp->clk_adjust;
  52. popts->wrlvl_start = pbsp->wrlvl_start;
  53. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  54. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  55. goto found;
  56. }
  57. pbsp_highest = pbsp;
  58. }
  59. pbsp++;
  60. }
  61. if (pbsp_highest) {
  62. printf("Error: board specific timing not found for %lu MT/s\n",
  63. ddr_freq);
  64. printf("Trying to use the highest speed (%u) parameters\n",
  65. pbsp_highest->datarate_mhz_high);
  66. popts->clk_adjust = pbsp_highest->clk_adjust;
  67. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  68. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  69. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  70. } else {
  71. panic("DIMM is not supported by this board");
  72. }
  73. found:
  74. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  75. "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  76. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  77. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  78. pbsp->wrlvl_ctl_3);
  79. popts->half_strength_driver_enable = 0;
  80. /*
  81. * Write leveling override
  82. */
  83. popts->wrlvl_override = 1;
  84. popts->wrlvl_sample = 0xf;
  85. /* Enable ZQ calibration */
  86. popts->zq_en = 1;
  87. /* Enable DDR hashing */
  88. popts->addr_hash = 1;
  89. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
  90. #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  91. fsl_ddr_setup_0v9_volt(popts);
  92. #endif
  93. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
  94. DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
  95. }
  96. #ifdef CONFIG_TFABOOT
  97. int fsl_initdram(void)
  98. {
  99. gd->ram_size = tfa_get_dram_size();
  100. if (!gd->ram_size)
  101. gd->ram_size = fsl_ddr_sdram_size();
  102. return 0;
  103. }
  104. #else
  105. int fsl_initdram(void)
  106. {
  107. puts("Initializing DDR....using SPD\n");
  108. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  109. gd->ram_size = fsl_ddr_sdram_size();
  110. #else
  111. gd->ram_size = fsl_ddr_sdram();
  112. #endif
  113. return 0;
  114. }
  115. #endif /* CONFIG_TFABOOT */