eth.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2018-2020 NXP
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <net.h>
  9. #include <asm/io.h>
  10. #include <netdev.h>
  11. #include <fdt_support.h>
  12. #include <fm_eth.h>
  13. #include <fsl_mdio.h>
  14. #include <fsl_dtsec.h>
  15. #include <malloc.h>
  16. #include <asm/arch/fsl_serdes.h>
  17. #include "../common/qixis.h"
  18. #include "../common/fman.h"
  19. #include "ls1046aqds_qixis.h"
  20. #define EMI_NONE 0xFF
  21. #define EMI1_RGMII1 0
  22. #define EMI1_RGMII2 1
  23. #define EMI1_SLOT1 2
  24. #define EMI1_SLOT2 3
  25. #define EMI1_SLOT4 4
  26. static int mdio_mux[NUM_FM_PORTS];
  27. static const char * const mdio_names[] = {
  28. "LS1046AQDS_MDIO_RGMII1",
  29. "LS1046AQDS_MDIO_RGMII2",
  30. "LS1046AQDS_MDIO_SLOT1",
  31. "LS1046AQDS_MDIO_SLOT2",
  32. "LS1046AQDS_MDIO_SLOT4",
  33. "NULL",
  34. };
  35. /* Map SerDes 1 & 2 lanes to default slot. */
  36. static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};
  37. static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)
  38. {
  39. return mdio_names[muxval];
  40. }
  41. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  42. {
  43. struct mii_dev *bus;
  44. const char *name;
  45. if (muxval > EMI1_SLOT4)
  46. return NULL;
  47. name = ls1046aqds_mdio_name_for_muxval(muxval);
  48. if (!name) {
  49. printf("No bus for muxval %x\n", muxval);
  50. return NULL;
  51. }
  52. bus = miiphy_get_dev_by_name(name);
  53. if (!bus) {
  54. printf("No bus by name %s\n", name);
  55. return NULL;
  56. }
  57. return bus;
  58. }
  59. struct ls1046aqds_mdio {
  60. u8 muxval;
  61. struct mii_dev *realbus;
  62. };
  63. static void ls1046aqds_mux_mdio(u8 muxval)
  64. {
  65. u8 brdcfg4;
  66. if (muxval < 7) {
  67. brdcfg4 = QIXIS_READ(brdcfg[4]);
  68. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  69. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  70. QIXIS_WRITE(brdcfg[4], brdcfg4);
  71. }
  72. }
  73. static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
  74. int regnum)
  75. {
  76. struct ls1046aqds_mdio *priv = bus->priv;
  77. ls1046aqds_mux_mdio(priv->muxval);
  78. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  79. }
  80. static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
  81. int regnum, u16 value)
  82. {
  83. struct ls1046aqds_mdio *priv = bus->priv;
  84. ls1046aqds_mux_mdio(priv->muxval);
  85. return priv->realbus->write(priv->realbus, addr, devad,
  86. regnum, value);
  87. }
  88. static int ls1046aqds_mdio_reset(struct mii_dev *bus)
  89. {
  90. struct ls1046aqds_mdio *priv = bus->priv;
  91. return priv->realbus->reset(priv->realbus);
  92. }
  93. static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
  94. {
  95. struct ls1046aqds_mdio *pmdio;
  96. struct mii_dev *bus = mdio_alloc();
  97. if (!bus) {
  98. printf("Failed to allocate ls1046aqds MDIO bus\n");
  99. return -1;
  100. }
  101. pmdio = malloc(sizeof(*pmdio));
  102. if (!pmdio) {
  103. printf("Failed to allocate ls1046aqds private data\n");
  104. free(bus);
  105. return -1;
  106. }
  107. bus->read = ls1046aqds_mdio_read;
  108. bus->write = ls1046aqds_mdio_write;
  109. bus->reset = ls1046aqds_mdio_reset;
  110. sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));
  111. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  112. if (!pmdio->realbus) {
  113. printf("No bus with name %s\n", realbusname);
  114. free(bus);
  115. free(pmdio);
  116. return -1;
  117. }
  118. pmdio->muxval = muxval;
  119. bus->priv = pmdio;
  120. return mdio_register(bus);
  121. }
  122. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  123. enum fm_port port, int offset)
  124. {
  125. struct fixed_link f_link;
  126. const char *phyconn;
  127. if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  128. switch (port) {
  129. case FM1_DTSEC9:
  130. fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1");
  131. break;
  132. case FM1_DTSEC10:
  133. fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2");
  134. break;
  135. case FM1_DTSEC5:
  136. fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3");
  137. break;
  138. case FM1_DTSEC6:
  139. fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4");
  140. break;
  141. case FM1_DTSEC2:
  142. fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1");
  143. break;
  144. default:
  145. break;
  146. }
  147. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
  148. /* 2.5G SGMII interface */
  149. f_link.phy_id = cpu_to_fdt32(port);
  150. f_link.duplex = cpu_to_fdt32(1);
  151. f_link.link_speed = cpu_to_fdt32(1000);
  152. f_link.pause = 0;
  153. f_link.asym_pause = 0;
  154. /* no PHY for 2.5G SGMII on QDS */
  155. fdt_delprop(fdt, offset, "phy-handle");
  156. fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
  157. fdt_setprop_string(fdt, offset, "phy-connection-type",
  158. "sgmii-2500");
  159. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
  160. switch (port) {
  161. case FM1_DTSEC1:
  162. fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4");
  163. break;
  164. case FM1_DTSEC5:
  165. fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2");
  166. break;
  167. case FM1_DTSEC6:
  168. fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1");
  169. break;
  170. case FM1_DTSEC10:
  171. fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3");
  172. break;
  173. default:
  174. break;
  175. }
  176. fdt_delprop(fdt, offset, "phy-connection-type");
  177. fdt_setprop_string(fdt, offset, "phy-connection-type",
  178. "qsgmii");
  179. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
  180. (port == FM1_10GEC1 || port == FM1_10GEC2)) {
  181. phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
  182. if (is_backplane_mode(phyconn)) {
  183. /* Backplane KR mode: skip fixups */
  184. printf("Interface %d in backplane KR mode\n", port);
  185. } else {
  186. /* XFI interface */
  187. f_link.phy_id = cpu_to_fdt32(port);
  188. f_link.duplex = cpu_to_fdt32(1);
  189. f_link.link_speed = cpu_to_fdt32(10000);
  190. f_link.pause = 0;
  191. f_link.asym_pause = 0;
  192. /* no PHY for XFI */
  193. fdt_delprop(fdt, offset, "phy-handle");
  194. fdt_setprop(fdt, offset, "fixed-link", &f_link,
  195. sizeof(f_link));
  196. fdt_setprop_string(fdt, offset, "phy-connection-type",
  197. "xgmii");
  198. }
  199. }
  200. }
  201. void fdt_fixup_board_enet(void *fdt)
  202. {
  203. int i;
  204. for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
  205. switch (fm_info_get_enet_if(i)) {
  206. case PHY_INTERFACE_MODE_SGMII:
  207. case PHY_INTERFACE_MODE_QSGMII:
  208. switch (mdio_mux[i]) {
  209. case EMI1_SLOT1:
  210. fdt_status_okay_by_alias(fdt, "emi1-slot1");
  211. break;
  212. case EMI1_SLOT2:
  213. fdt_status_okay_by_alias(fdt, "emi1-slot2");
  214. break;
  215. case EMI1_SLOT4:
  216. fdt_status_okay_by_alias(fdt, "emi1-slot4");
  217. break;
  218. default:
  219. break;
  220. }
  221. break;
  222. default:
  223. break;
  224. }
  225. }
  226. }
  227. int board_eth_init(struct bd_info *bis)
  228. {
  229. #ifdef CONFIG_FMAN_ENET
  230. int i, idx, lane, slot, interface;
  231. struct memac_mdio_info dtsec_mdio_info;
  232. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  233. u32 srds_s1, srds_s2;
  234. u8 brdcfg12;
  235. srds_s1 = in_be32(&gur->rcwsr[4]) &
  236. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  237. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  238. srds_s2 = in_be32(&gur->rcwsr[4]) &
  239. FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
  240. srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
  241. /* Initialize the mdio_mux array so we can recognize empty elements */
  242. for (i = 0; i < NUM_FM_PORTS; i++)
  243. mdio_mux[i] = EMI_NONE;
  244. dtsec_mdio_info.regs =
  245. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  246. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  247. /* Register the 1G MDIO bus */
  248. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  249. /* Register the muxing front-ends to the MDIO buses */
  250. ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
  251. ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
  252. ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  253. ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
  254. ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  255. /* Set the two on-board RGMII PHY address */
  256. fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
  257. fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
  258. switch (srds_s1) {
  259. case 0x3333:
  260. /* SGMII on slot 1, MAC 9 */
  261. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  262. case 0x1333:
  263. case 0x2333:
  264. /* SGMII on slot 1, MAC 10 */
  265. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  266. case 0x1133:
  267. case 0x2233:
  268. /* SGMII on slot 1, MAC 5/6 */
  269. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  270. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  271. break;
  272. case 0x1040:
  273. case 0x2040:
  274. /* QSGMII on lane B, MAC 6/5/10/1 */
  275. fm_info_set_phy_address(FM1_DTSEC6,
  276. QSGMII_CARD_PORT1_PHY_ADDR_S2);
  277. fm_info_set_phy_address(FM1_DTSEC5,
  278. QSGMII_CARD_PORT2_PHY_ADDR_S2);
  279. fm_info_set_phy_address(FM1_DTSEC10,
  280. QSGMII_CARD_PORT3_PHY_ADDR_S2);
  281. fm_info_set_phy_address(FM1_DTSEC1,
  282. QSGMII_CARD_PORT4_PHY_ADDR_S2);
  283. break;
  284. case 0x3363:
  285. /* SGMII on slot 1, MAC 9/10 */
  286. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  287. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  288. case 0x1163:
  289. case 0x2263:
  290. case 0x2223:
  291. /* SGMII on slot 1, MAC 6 */
  292. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  293. break;
  294. default:
  295. printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
  296. srds_s1);
  297. break;
  298. }
  299. if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
  300. /* SGMII on slot 4, MAC 2 */
  301. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  302. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  303. idx = i - FM1_DTSEC1;
  304. interface = fm_info_get_enet_if(i);
  305. switch (interface) {
  306. case PHY_INTERFACE_MODE_SGMII:
  307. case PHY_INTERFACE_MODE_QSGMII:
  308. if (interface == PHY_INTERFACE_MODE_SGMII) {
  309. if (i == FM1_DTSEC5) {
  310. /* route lane 2 to slot1 so to have
  311. * one sgmii riser card supports
  312. * MAC5 and MAC6.
  313. */
  314. brdcfg12 = QIXIS_READ(brdcfg[12]);
  315. QIXIS_WRITE(brdcfg[12],
  316. brdcfg12 | 0x80);
  317. }
  318. lane = serdes_get_first_lane(FSL_SRDS_1,
  319. SGMII_FM1_DTSEC1 + idx);
  320. } else {
  321. /* clear the bit 7 to route lane B on slot2. */
  322. brdcfg12 = QIXIS_READ(brdcfg[12]);
  323. QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
  324. lane = serdes_get_first_lane(FSL_SRDS_1,
  325. QSGMII_FM1_A);
  326. lane_to_slot[lane] = 2;
  327. }
  328. if (i == FM1_DTSEC2)
  329. lane = 5;
  330. if (lane < 0)
  331. break;
  332. slot = lane_to_slot[lane];
  333. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  334. idx + 1, slot);
  335. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  336. fm_disable_port(i);
  337. switch (slot) {
  338. case 1:
  339. mdio_mux[i] = EMI1_SLOT1;
  340. fm_info_set_mdio(i, mii_dev_for_muxval(
  341. mdio_mux[i]));
  342. break;
  343. case 2:
  344. mdio_mux[i] = EMI1_SLOT2;
  345. fm_info_set_mdio(i, mii_dev_for_muxval(
  346. mdio_mux[i]));
  347. break;
  348. case 4:
  349. mdio_mux[i] = EMI1_SLOT4;
  350. fm_info_set_mdio(i, mii_dev_for_muxval(
  351. mdio_mux[i]));
  352. break;
  353. default:
  354. break;
  355. }
  356. break;
  357. case PHY_INTERFACE_MODE_RGMII:
  358. case PHY_INTERFACE_MODE_RGMII_TXID:
  359. if (i == FM1_DTSEC3)
  360. mdio_mux[i] = EMI1_RGMII1;
  361. else if (i == FM1_DTSEC4)
  362. mdio_mux[i] = EMI1_RGMII2;
  363. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  364. break;
  365. default:
  366. break;
  367. }
  368. }
  369. cpu_eth_init(bis);
  370. #endif /* CONFIG_FMAN_ENET */
  371. return pci_eth_init(bis);
  372. }